Power semiconductor device comprising vertical double-diffused M

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257401, 257382, 257341, H01L 2976, H01L 2994, H01L 31062

Patent

active

055214100

ABSTRACT:
In a vertical double-diffused MOSFET comprising a semiconductor substrate of a first conductivity type, an epitaxial layer of the first conductivity type, and a gate insulating layer, a gate electrode coats the gate insulating layer. The gate electrode has a plurality of polygonal shaped opening windows and at least one slit shaped opening window. Each polygonal shaped opening window has a center positioned on each of lattice points of a two-dimensional square lattice comprising a plurality of unit cells. Each slit shaped opening window is laid on a straight line connecting two centers of two polygonal shaped opening windows which are obliquely adjacent to one another. A first insulating layer is formed on an upper surface of the gate electrode. Second insulating layers are formed on side walls of the gate electrode. A base region of a second conductivity type having a base junction depth is formed in the surface of the epitaxial layer. The base region is self-aligned to the polygonal shaped opening windows and the slit shaped opening window. A source region of the first conduction type has a source junction depth shallower than the base junction depth. The source region has an inner edge self-aligned to both of the polygonal shaped opening windows and the slit shaped opening window and an inner edge spaced apart from the polygonal shaped open windows at a predetermined width.

REFERENCES:
patent: 5008725 (1991-04-01), Lidow et al.
patent: 5016066 (1991-05-01), Takahashi
patent: 5408118 (1995-07-01), Yamamoto
Sun S. C. and Plummber, James D., "Modeling Of The On-Resistance of LDMOS, VDMOS, And VMOS Power Transistors", IEEE Transactions on Electron Devices, vol. ED-27, No. 2 Feb., 1990, pp. 356-367.

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