Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-09-15
2004-10-12
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S327000, C257S328000, C257S329000, C257S330000, C257S331000, C257S335000, C257S341000
Reexamination Certificate
active
06803628
ABSTRACT:
INCORPORATION BY REFERENCE
The disclosure of Japanese Patent Application No. HEI 11-262861 filed on Sep. 17, 1999 including the specification, drawings and abstract is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a power semiconductor device and a production method for the power semiconductor device and, more particularly, to a power semiconductor device having a plurality of linear trench gates that extend substantially parallel to one another and extend through a body region formed on a semiconductor substrate, from an obverse surface side of the body region.
2. Description of the Related Art
As a power semiconductor device, an insulated gate bipolar transistor (IGBT) in which N-type emitters formed in contact with trench gates are connected by N-type semiconductor regions so as to form a ladder-shaped configuration has been proposed (e.g., in Japanese Patent Application Laid-Open No. HEI 9-270512). In this device, the emitter-contact width is reduced by forming ladder-shaped N-type semiconductor regions. In this device, the N-type emitters and the N-type semiconductor regions are formed by a single diffusion layer, and therefore, their depths are substantially equal.
In power semiconductor devices, both low on-resistance and high breakdown ruggedness are demanded.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a power semiconductor device with low on-resistance and high breakdown ruggedness.
An insulated gate type semiconductor device according to the invention includes a body region of a first conductivity type formed in a semiconductor substrate, a plurality of trench gates extending through the body region, and a plurality of first semiconductor regions of a second conductivity type that is different from the first conductivity type. The first semiconductor regions have a first depth as measured from a surface of the body region and sandwich the trench gates via the gate-insulating films. The semiconductor device also includes a plurality of second semiconductor regions of the second conductivity type having a second depth as measured from the surface of the body region that is less than the first depth. The second semiconductor regions connect the plurality of first semiconductor regions spaced apart from one another.
According to the above-described aspect, since the second semiconductor regions are formed to have less depth than the first semiconductor regions, the impurity concentration in a portion of the body region near the second semiconductor region can be increased, in comparison with a case where the first and second semiconductor regions have substantially equal depths. Therefore, the resistance in the portion of the body region near the second semiconductor region is decreased, so that the on-resistance of the semiconductor device can be reduced and the breakdown ruggedness thereof can be improved.
REFERENCES:
patent: 5502320 (1996-03-01), Yamada
patent: 5648670 (1997-07-01), Blanchard
patent: 5986304 (1999-11-01), Hshieh et al.
patent: 6096608 (2000-08-01), Williams
patent: 6111283 (2000-08-01), Yang et al.
patent: 63-50071 (1988-03-01), None
patent: 7-235672 (1995-05-01), None
patent: 9-270512 (1997-10-01), None
patent: 10-150191 (1998-06-01), None
M. Kato et al, “A 0.4 micrometer-squared Self-Aligned Contactless Memory Cell Technology Suitable for 256-Mbit Flash Memories”, Electron Dev. Mtg. '94, Techn. Digest pp. 921-923, Dec. 11-14, 1994, San Francisco, USA (ISBN: 0-7803-2111-1).
Flynn Nathan J.
Mondt Johannes
Pillsbury & Winthrop LLP
LandOfFree
Power semiconductor device and production method for the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Power semiconductor device and production method for the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power semiconductor device and production method for the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3276300