Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-12-11
2002-12-24
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S345000, C257S401000
Reexamination Certificate
active
06498368
ABSTRACT:
BACKGROUND OF THE INVENTION
In known semiconductor devices, in cases where the terminals of the main current path are used as first and second terminals to give the semiconductor devices a high withstanding-voltage, it is necessary to form a depletion layer so that the strength of an electric field generated inside of the semiconductor element, when a voltage is impressed between the first terminal and the second terminal, becomes lower than the critical strength, resulting in avalanche breakdown. To this end, it is necessary to make the specific resistance of a drift layer area high and to form the drift layer area so that the length thereof in the voltage drop direction is large, so that the depletion layer can easily spread when a voltage is applied between the first and second terminals. Therefore, there is a problem that the resistance between the first terminal and the second terminal raises rapidly as the withstanding-voltage between the first terminal and the second terminal is made higher.
Japanese Patent Prepublication No. 54661/1990 discloses a semiconductor device in which the semiconductor main body has a plurality of n-type first regions, between which a p-type second region is sandwiched. The length of these first and second regions in the direction perpendicular to their thickness is made to have a value sufficient to carry a voltage over 100V along the semiconductor main body when a free charge carrier was eliminated, and an electrically parallel current path is formed which extends through the semiconductor main body. The values of the thickness and doping density of each of the first and second regions are selected so that the space-charge per unit area of each of positive and negative alternately arranged space-charge regions formed by the first and second regions becomes lower than the critical strength, resulting in avalanche breakdown.
Further, in the above-mentioned Japanese Patent Prepublication No. 54661/1990, a semiconductor device is also disclosed in which, in order to form said first and second regions, a high resistance p-type epitaxial layer is grown on a low ohmic n-type substrate having a main surface axial direction of [
110
], and etching is performed until reaching the substrate by using anisotropic etching. A groove is formed having sheer side faces in the epitaxial layer, and then an n-type epitaxial layer is formed, and this n-type epitaxial layer is used as said first regions and said high resistance p-type epitaxial layer is used as said second regions. Although in the above-mentioned Japanese Patent Prepublication No. 54661/1990 there is a description indicating that anisotropic etching is applied to the (
110
) face, and thereby the repeated pattern of n-type and p-type regions can be formed, no planar structure suitable for low loss is discussed. Also, in the case of the semiconductor elements in the above-mentioned Japanese Patent Prepublication No. 54661/1990, since it is impossible to make the repeated pattern of the n-type and p-type regions narrow, there is the problem that it is impossible to make the electric power consumed in the semiconductor element; and, further, because of the existence of said repeated pattern, there is the problem that the inter-drain/source capacitance of a power MOS FET, for example, becomes large.
In U.S. Pat. No. 5,438,215 and U.S. Pat. No. 5,216,275, there is disclosed a planer structure suitable to provide a semiconductor device best suited to a high withstanding-voltage and low loss. However, in U.S. Pat. No. 5,438,215 and U.S. Pat. No. 5,216,275, there is no description relating to the planer structure suitable for the case where the (
110
) face is used as the semiconductor substrate.
Japanese Patent Prepublication No. 223896/1998 proposes a method for ion implantation into the side faces of etched silicon grooves, as a method of manufacture of a semiconductor device simultaneously achieving low loss and a high withstanding-voltage. However, although Japanese Patent Prepublication No. 54661/1998 describes an approach for making the pitch of the repeated pattern of the n-type and p-type regions narrow, this structure is in effect unsuitable for production.
German Patent No. 19730759 discloses a structure in which said p-type second regions are separated from the body diffusion layer of a MOS FET. In the technique disclosed in this German Patent No. 19730759, in order to obtain a device structure suitable for a high withstanding-voltage and a low loss, there is a need for an improvement.
SUMMARY OF THE INVENTION
The semiconductor device according to this invention comprises a voltage holding area in which, within the semiconductor chip, first regions of a first conduction type having an elongated shape and second regions of a second conduction type having a similar shape are arranged alternately and adjacently. The first regions are connected to a second terminal and the second regions are connected to a first terminal. When a voltage is applied between the first and second terminals and current flow is obstructed, positive and negative space-charge regions are alternately arranged in the voltage holding area formed by the first and second regions. In this case, the first and second conduction are the p-type or the n-type, respectively, which are opposite conduction types. Furthermore, the semiconductor device according to this invention can have one construction selected from the following descriptions A to E:
A. A device in which the substrate main surface of the semiconductor chip is positioned on the (
110
) face and a couple of opposed side edges of four side edges of the semiconductor chip are positioned on the {
111
} face, which is perpendicular to the (
110
) face, and the first and second regions extend in an elongated fashion in the [
110
] axis direction.
B. A device in which the substrate main surface of the semiconductor chip is positioned on the (
110
) face, and the first and second regions extend in an elongated fashion in the [
110
] axis direction, with the main contact face positioned on the {
111
} face perpendicular to (
110
) face.
C. A device in which a third regions of the first conduction type are formed at the periphery of the voltage holding area, said third regions having a higher mean impurity concentration than that of the first regions.
D. The semiconductor device is an insulated gate type semiconductor device of which channel region is separated from the second regions.
E. The semiconductor device is an insulated gate type semiconductor device of a trench gate type, which the spacing between the trench gates is shorter than the spacing between the second regions.
A method of manufacturing a semiconductor device having the construction A or B, according to this invention includes the following steps F or G:
F. A step of forming a groove in the silicon semiconductor chip with an anisotropic etching liquid by using as a mask a polygon pattern composed of four main sides intersecting at the angle of 70.5°±5° or 109.5°±5°, and a step of filling the formed groove with a silicon layer.
G. A step of forming a groove in said silicon semiconductor chip with an isotropic etching liquid by using a photo mask formed along the (-
11
-
1
) face or the (-
11
-
1
) face on which a couple of opposed side edges out of four side edges of said semiconductor chip are positioned, and a step of filling the formed groove with a silicon layer.
In accordance with this invention, the voltage holding area can be formed with high precision, or it is possible to improve the voltage holding function of the voltage holding area at the time when current flow is obstructed. Therefore, it is possible to achieve a semiconductor device with a high withstanding-voltage and/or a low loss function.
REFERENCES:
patent: 4065742 (1977-12-01), Kendall et al.
patent: 4268848 (1981-05-01), Casey et al.
patent: 5216275 (1993-06-01), Chen
patent: 5438215 (1995-08-01), Tihanyi
patent: 6326656 (2001-12-01), Tihanyi
patent: 6344379 (2002-02-01),
Inoue Yosuke
Miyauchi Akihiro
Mori Mutsuhiro
Ohyanagi Takasumi
Sakamoto Kozo
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Ngo Ngan V.
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