Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-07
2001-10-02
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S401000, C438S156000, C438S268000
Reexamination Certificate
active
06297534
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power semiconductor device having a lateral power MOSFET.
2. Discussion of the Background
A lateral power MOSFET as one of high withstand voltage elements to be used in a power semiconductor device is known.
FIG. 10
shows a sectional perspective view of a background lateral power MOSFET.
FIG. 11
shows a plan view of the same lateral power MOSFET,
FIG. 12
a sectional view taken along line A-A′ in
FIG. 11
,
FIG. 13
a sectional view taken along line B-B′ in
FIG. 11
, and
FIG. 14
a sectional view taken along line C-C′ in FIG.
11
.
The background lateral power MOSFET includes drift layers formed in a stripe form having n
−
semiconductor layers
81
(described as n
−
drift layers
81
) and p
−
semiconductor layers
82
(described as p
−
drift layers
82
) alternately formed along a channel width direction. The alternately formed structure having the n
−
drift layers
81
and p
−
drift layers
82
as such is referred to as a multi-resurf layer.
In
FIGS. 10
to
14
,
83
represents a support substrate,
84
a buried oxide film,
85
an n
−
active layer,
86
a p body layer,
87
an n
+
source diffusion layer,
88
a p
+
contact layer,
89
a gate oxide film,
90
a gate electrode,
91
an n
+
drain diffusion layer,
92
a drain electrode, and
93
a source electrode.
In the structure as described above, a voltage below a threshold voltage, for example 0 V or a negative voltage, is applied to the gate electrode
90
. The source electrode
93
is provided with the same voltage as the gate electrode
90
. A voltage higher than that applied to the gate electrode
90
and lower than that applied to the drain electrode
92
may be applied to the source electrode
93
to turn off the device. Thereupon, a depletion layer
94
possibly occurs from a pn junction interface of a n
−
drift layer
81
and a p
−
drift layer
82
, as shown in FIG.
11
.
The drift layers
81
,
82
are narrow in stripe width. Accordingly, complete depletion readily occurs as compared to a structure without p
−
drift layers
82
, i.e., as compared to a structure to cause complete depletion of the drift layers due to depletion directed from the gate electrode
90
toward the n
+
drain layer
91
. This allows the drift layers
81
to have an increased impurity dosage, and to hence reduce ON resistance.
On the other hand, as shown in
FIG. 12
, a depletion layer
95
also occurs from an interface of the buried oxide film
84
and the n
−
drift layers
81
. When the depletion layer
95
spreads over the entire n
−
drift layers
81
, the depletion layer
94
stops spreading.
If the p
−
drift layers
82
have not been completely depleted, undepleted regions will be left in part of the p
−
drift layers
82
. In particular, as shown in
FIG. 12
, undepleted regions are liable to occur in a lower portion
96
of the p
−
drift layers
82
. The undepleted regions, if left, cause a problem that high withstand voltage as expected is not obtainable.
As discussed above, although the background lateral power MOSFET having the n
−
drift layers and the p
−
drift layers (multi-resurf layer) have had the advantage of reducing ON resistance to be low, there has been a problem that high withstand voltage as expected is not obtainable due to undepleted regions left in part of the p
−
drift layers.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a power semiconductor device provided with a lateral power MOSFET having n
−
drift layers and p
−
drift layers and which has a low ON resistance and high withstand voltage.
To achieve the above and other objects, a power semiconductor device according to the present invention includes: a first conductivity type active layer provided on an insulation region and having high resistance; a second conductivity type base layer selectively formed on a surface of the first conductivity type active layer; a first conductivity type source layer selectively formed on a surface of the second conductivity type base layer; a first conductivity type drain layer selectively formed on a surface of the first conductivity type active layer; a gate electrode facing, through a gate insulating film, a surface region of the second conductivity type base layer between the first conductivity type source layer and the first conductivity type active layer; and, a plurality of first and second conductivity type semiconductor regions formed between the second conductivity type base layer and the first conductivity type drain layer. Further, each of the second conductivity type semiconductor regions is arranged alternately with each of the first conductivity type semiconductor regions. A drain current flows from the first conductivity type source layer to the first conductivity type drain layer through the first conductivity type semiconductor regions. Bottom portions of the second conductivity type semiconductor regions are shallower than the interface between the first conductivity type active layer and the insulation region.
Also, another power semiconductor device according to the present invention includes: a first conductivity type active layer provided on an insulation region and having high resistance; a second conductivity type base layer selectively formed on a surface of the first conductivity type active layer; a first conductivity type source layer selectively formed on a surface of the second conductivity type base layer; a first conductivity type drain layer selectively formed on a surface of the first conductivity type active layer; a gate electrode facing, through a gate insulating film, a surface region of the second conductivity type base layer between the first conductivity type source layer and the first conductivity type active layer; and, a plurality of first and second conductivity type semiconductor regions formed between the second conductivity type base layer and the first conductivity type drain layer and formed above the insulation region with the first conductivity type active layer therebetween. Each of the second conductivity type semiconductor regions is arranged alternately with each of the first conductivity type semiconductor regions and is arranged in a direction crossing a direction from the first conductivity type source layer to the first conductivity type drain layer.
Also, another power semiconductor device according to the present invention includes: a first conductivity type active layer provided on an insulation region and having high resistance; a second conductivity type base layer selectively formed on a surface of the first conductivity type active layer; a first conductivity type source layer selectively formed on a surface of the second conductivity type base layer; a first conductivity type drain layer selectively formed on a surface of the first conductivity type active layer; a gate electrode facing, through a gate insulating film, a surface region of the second conductivity type base layer between the first conductivity type source layer and the first conductivity type active layer; and, a plurality of first and second conductivity type semiconductor regions formed between the second conductivity type base layer and the first conductivity type drain layer and formed on a surface of the first conductivity type active layer. Each of the second conductivity type semiconductor regions is arranged alternately with each of the first conductivity type semiconductor regions. A drain current flows from the first conductivity type source layer to the first conductivity type drain layer through the first conductivity type semiconductor regions. The plurality of first and second conductivity type semiconductor regions are completely depleted from junction interfaces thereof before a depletion layer extending from a surface of the insulation region reaches bottom portions of the
Kawaguchi Yusuke
Nakagawa Akio
Nakamura Kazutoshi
Flynn Nathan
Forde Remmon R.
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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