Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-02-20
2010-11-23
Chase, Shelly A (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
07840876
ABSTRACT:
The present invention includes a memory device with a data memory and an error correction code control circuit. The data memory stores data parity information for error correction. The error correction code control circuit is configured to receive a selection signal indicative of whether an error correction mode is to be used. Power to access the portion of the memory storing the parity information is disabled when the error correction mode is enabled.
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Streif Harald
Sturm Andre
Chase Shelly A
Coats & Bennett P.L.L.C.
Qimonda AG
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