Power saving semsing circuits for dynamic random access memory

Details Power saving semsing circuits for dynamic random access memory Power saving semsing circuits for dynamic random access memory

1991-07-12

1994-01-18

Pascal, Robert J.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

365208, 365227, G11C 700, G11C 1140

Patent

active

052804526

ABSTRACT:
A sensing circuit for a dynamic random access memory structure is disclosed having first and second bit lines, one of the bit lines being a reference bit line which is held at a precharge voltage when a sense amplifier in the sensing circuit is latched, the sense amplifier includes first and second nodes and first, second, third and fourth transistor devices, the first and second transistor devices form an N-device cross-coupled pair and the third and fourth transistor devices form a P-device cross-coupled pair. The first node is connected to the first bit line and to the second and fourth transistor devices, and the second node is connected to the first and third transistor devices. A first isolation transistor device is connected to the first bit line and a second isolation transistor device is connected to the second bit line. A first clock signal line is connected to the first isolation transistor device and a second clock signal line is connected to the second isolation transistor device. A first equalization transistor device is connected to the first bit line and a second equalization transistor device is connected to the second bit line, a voltage signal line having a voltage value V.sub.EQ thereon is connected to the first and second equalization transistor devices, and a third clock signal line is connected to the first equalization device. A fourth clock signal line is connected to the second equalization transistor device, a fifth clock signal line is connected to the first and second N devices, a sixth clock signal line is connected to the third and fourth P devices. The first, second, third, fourth and fifth and sixth clock signal lines have clock signals thereon which occur during a time sequence for precharging the first and second nodes to a precharge voltage value V.sub.EQ.

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