Power saving refresh scheme for DRAMs with segmented word...

Details Power saving refresh scheme for DRAMs with segmented word... Power saving refresh scheme for DRAMs with segmented word...

2007-01-30

2007-01-30

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S149000, C365S230030, C365S239000

Reexamination Certificate

active

11089860

ABSTRACT:
Techniques and apparatus that may be utilized to reduce current consumption during refresh cycles of DRAM devices that utilize wordline segments are provided. Rather than activate and subsequently de-activate (pre-charge) a master wordline each time a corresponding wordline segment is refreshed, the master wordline may remain activated while corresponding wordline segments are refreshed.

REFERENCES:
patent: 4758993 (1988-07-01), Takemae
patent: 4933907 (1990-06-01), Kumanoya et al.
patent: 5251176 (1993-10-01), Komatsu
patent: 5631872 (1997-05-01), Naritake et al.
patent: 5822264 (1998-10-01), Tomishima et al.
patent: 6570801 (2003-05-01), Yoshida et al.
patent: 6934211 (2005-08-01), Hazama et al.
patent: 6982917 (2006-01-01), Lee et al.

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