Power-saving clocking technique

Details Power-saving clocking technique Power-saving clocking technique

2007-03-23

2010-12-07

Du, Thuan N (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S323000, C713S324000, C713S600000, C327S117000, C327S156000

Reexamination Certificate

active

07849339

ABSTRACT:
A method and system for providing a clock signal having reduced power consumption is provided, called the hybrid clock system. The hybrid clock system uses a PLL for high-speed data transfers, but provides a power-saving mode for transferring data while consuming less power. In the normal mode, the hybrid clock system contains a reference clock that operates at a low frequency that drives a PLL. The PLL multiplies the reference clock frequency to a much higher frequency, and supplies the clock signal to a data transfer circuit. In the power-saving mode, the hybrid clock system turns off the PLL and connects the reference clock directly to the data transfer circuit.

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