Power saving circuitry using predictive logic

Details Power saving circuitry using predictive logic Power saving circuitry using predictive logic

2001-09-28

2003-07-15

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

C327S012000, C327S003000, C327S158000, C327S107000

Reexamination Certificate

active

06593773

ABSTRACT:

STATEMENT OF FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates in general to integrated circuits and, more particularly, to a method and apparatus for reducing power consumption in an integrated circuit for frequency synthesis.
2. Description of the Related Art
A great reduction of the transistor features in recently developed deep-submicron CMOS processes shifts the design paradigm towards more digitally-intensive techniques. In a monolithic implementation, the manufacturing cost of a design is measured not in terms of a number of devices used but rather in terms of the occupied silicon area, no matter what the actual circuit complexity.
Analog and RF circuits used in communication circuits, however, are not easily implemented in a deep-submicron CMOS process. For example, in Texas Instruments' CMOS process (C035) of 0.08 &mgr;m L-effective features a digital gate density of 150K equivalent (2-input NAND) gates per mm
2
. An average-size inductor for an integrated LC oscillator occupies about 0.5 mm
2
of silicon area. A low-noise charge pump, or a low-distortion image-reject modulator, both good examples of classical RF transceiver components, occupy roughly about the same area, which could be traded for tens of thousands of digital gates.
Migrating to a digitally-intensive synthesizer architecture brings forth the following well-known advantages: (1) fast design turn-around cycle using automated CAD tools (VHDL or Verilog hardware-level description language, synthesis, auto-place and auto-route with timing-driven algorithms, parasitic backannotation and postlayout optimization), (2) much lower parameter variability than with analog circuits, (3) ease of testability, (4) lower silicon area and dissipated power that gets better with each CMOS technology advancement (also called a “process node”) and (5) excellent chances of first-time silicon success. Commercial analog circuits usually require several design iterations to meet marketing requirements.
Sensible integration of diverse sections results in a number of advantages: (1) lower total silicon area. In a deep-submicron CMOS design, the silicon area is often bond-pad limited; consequently, it is beneficial to merge various functions on a single silicon die to maximize the core to bond-pad ratio, (2) lower component count and thus lower packaging cost, (3) power reduction—no need to drive large external inter-chip connections and (4) lower printed-circuit board (PCB) area, thus saving the precious “real estate.”
While a digital implementation can reduce power consumption, it is still important for a digital design to be power efficient. In addition to environmental concerns over wasted energy resources, power efficiency is particularly important for battery-powered devices to maximize the time between battery replacement/recharging.
Therefore, a need has arisen for a method and apparatus for a power efficient digital circuit.
BRIEF SUMMARY OF THE INVENTION
In the present invention, a time-to-digital conversion is performed relative to a first signal and a second signal, wherein the first signal transitions between states rapidly with respect to the second signal. The first signal is passed to a string of logic devices during a time period sufficient to allow the first circuit to reach a desired state prior to an active edge of the second signal and is not passed during other time periods. A state associated with the string of logic devices is stored responsive to the active edge of a second signal.
The present invention provides a significant advantage over the prior art. Since the first signal is passed to the string of logic devices only during a time period where the active edge of the second signal may occur, the logic devices do not transition between states during periods where propagation of the first signal is unnecessary, thereby conserving power.


REFERENCES:
patent: 5128624 (1992-07-01), Hoshino et al.
patent: 5835552 (1998-11-01), Kusumoto et al.
patent: 6429693 (2002-08-01), Staszewski et al.

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