Power saving buffer circuit buffer bias voltages

Details Power saving buffer circuit buffer bias voltages Power saving buffer circuit buffer bias voltages

1996-12-16

1999-09-21

Tokar, Michael

Electronic digital logic circuitry

Interface

Logic level shifting

326 81, 326121, H03K 190175, H03K 19094

Patent

active

059558938

ABSTRACT:
An embodiment of the invention provides a buffer circuit having reduced power consumption. The buffer circuit comprises a power saving switch coupled to a buffer at a bias node. The buffer has an input that is adapted to receive input voltages at TTL levels, for example, and has an output adapted to provide output voltages at CMOS levels, for example. The power saving switch includes a level shifter and a voltage control circuit both coupled to the bias node. The output voltage of the buffer is fed back to the power saving switch. When the output voltage is at a low CMOS level, the power saving switch uses the voltage control circuit to provide a first bias voltage to the bias node. When the output voltage is at a high CMOS level, the power saving switch uses the level shifter to provide a second bias voltage to the bias node. The second bias voltage is chosen such that it prevents current flow between the bias node and the buffer at a predetermined input cutoff voltage. The level shifter provides a relatively constant second bias voltage by providing a relatively constant voltage shift V.sub.LS between a level shifter reference voltage V.sub.ref and the bias node. In the present embodiment, this voltage shift V.sub.LS is the absolute value of the gate to source threshold voltage of a FET. Accordingly, the second bias voltage is V.sub.ref -V.sub.LS. In one embodiment, the voltage control circuit includes a second level shifter to provide the first bias voltage.

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