Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
1999-11-30
2004-01-20
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S108000, C711S128000, C365S049130
Reexamination Certificate
active
06681312
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to address translation and more specifically to a translation lookaside buffer.
2. Description of the Related Art
In microprocessors, translation from a virtual address to a physical address is performed by an address translation buffer, called a translation lookaside buffer. This buffer has a first content-addressable memory array for comparison between previous process identifiers and a new process identifier for a first match and a second content-addressable memory array for comparison between previous virtual addresses and a new virtual address for a second match. When the first match is detected in one or more of the memories of the first memory array, those memories of the second memory array that correspond to the matched memories of the first memory array are triggered to execute a comparison between the previous virtual addresses and the new virtual address. In order to trigger the second memory array, a number of latches are provided for receiving output signals from corresponding memories of the first memory array and a corresponding number of drivers are connected to the outputs of the latches. When the comparison is being performed in the first memory array, all output lines of the drivers are pulled up to a high voltage level in response to a precharge signal. All output lines of the drivers are then pulled down to a low voltage level in response to a discharge signal except for those of the drivers where the corresponding latches have received output signals from the corresponding memories indicating the detection of the first match. The precharged states of the output lines where the first match is detected are maintained as match signals and used to trigger the second memory array for a match between virtual addresses.
Since all output lines of the drivers are pulled up to the precharge voltage regardless of the results of comparisons in the first memory array and those output lines where mismatch has occurred are then pulled down to the low voltage level, currents are discharged through the mismatched drivers. As a result, a substantial amount of energy is dissipated. Since this dissipated energy serves no purpose for the second memory array, a need exists to eliminate such lost energy.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a power saving address translation buffer that eliminates waste of energy when there is no match between the process identifier of a currently executed process and a stored process identifier.
According to a first aspect, the present invention provides an address translation buffer comprising a first memory array having a plurality of content-addressable memories, each memory storing a previous process identifier for comparing the previous process identifier with a new process identifier which identifies a currently executed process and producing a first output signal when a coincidence is detected between the previous and new process identifiers and a second output signal when a coincidence is not detected. A plurality of drivers are associated respectively with the memories of the first memory array, each of the drivers having an output line and pulling the output line to a first voltage level only when the first output signal from the associated memory coincides with a precharge signal to produce a match signal and pulling the output line to a second voltage level in response to a discharge signal when the associated memory of the first memory array is producing the second output signal. A second memory array having a plurality of content-addressable memories is provided corresponding respectively to the drivers. Each memory of the second memory array stores a previous virtual address and compares it with a new virtual address corresponding to the new process identifier in response to the match signal of the corresponding driver. If a coincidence is detected between the previous and new virtual addresses, an output signal is supplied from that memory of the second memory array to a third memory from which a corresponding one of physical addresses is selected for output delivery.
Preferably, each of the drivers a coincidence gate for producing a coincidence output when the output signal of the associated memory of the first memory array coincides with the precharge signal, a first transistor responsive to the coincidence output for pulling the output line to the first voltage level, a second, normally conducting transistor responsive to the output signal of the associated memory of the first memory for changing to a non-conducting state, and a third transistor responsive to the discharge signal for pulling the output line to the low voltage level via the second transistor when the second transistor is conducting.
Preferably, a second driver is provided. The second driver has a plurality of output bit lines for pulling the output bit lines to different voltage levels corresponding to respective bits of the new virtual address and pulling the output bit lines to the low voltage level only when the output signal of at least one of the memories of the first memory array coincides with the discharge signal. Each memory of the second memory array is connected to the output bit lines for comparing the previous virtual address with the new virtual address represented by the different voltage levels from the second driver in response to the match signal of the corresponding.
According to a second aspect, the present invention provides an address translation buffer comprising a first memory array having a plurality of content-addressable memories, each memory storing a process identifier for comparing the process identifier with a process identifier which identifies a currently executed process and producing an output signal when a coincidence is detected between the process identifiers, a plurality of first drivers associated respectively with the memories of the first memory array, each of the drivers producing a match signal in response to the output signal from the associated memory of the first memory array, a second driver having a plurality of output bit lines for pulling the output bit lines to different voltage levels corresponding to respective bits of a new virtual address associated with the new process identifier, and pulling the output bit lines to the low voltage level only when the output signal of at least one of the memories of the first memory array coincides with the discharge signal, a second memory array having a plurality of content-addressable memories corresponding respectively to the first drivers, each memory of the second memory array being connected to the output bit lines of the second driver for storing a previous virtual address and comparing the previous virtual address with a new virtual address represented by the different voltage levels of the second driver in response to the match signal of the corresponding first driver and producing an output signal when a coincidence is detected between the previous and new virtual addresses, and a third memory for storing a plurality of physical addresses associated respectively with the memories of the second memory array and delivering one of the physical addresses in response to the output signal of the associated memory of the second memory array.
REFERENCES:
patent: 5530822 (1996-06-01), Beavers et al.
patent: 5535351 (1996-07-01), Peng
patent: 63-81548 (1988-04-01), None
patent: 7-21785 (1995-01-01), None
Japanese Office Action with English translation of pertinent portions dated Oct. 23, 2002.
Anderson Matthew D.
Kim Matthew
NEC Electronics Corporation
Whitman Curtis & Christofferson, PC
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