Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-01-29
2004-06-29
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06757881
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to the field of integrated circuit design, and particularly to a system and method for power routing with obstacles in an integrated circuit.
BACKGROUND OF THE INVENTION
An integrated circuit chip (hereafter referred to as an “IC” or a “chip”) comprises cells and connections between the cells formed on a surface of a semiconductor substrate. The IC may include a large number of cells and require complex connections between the cells.
Microelectronic integrated circuits include a large number of electronic components that are fabricated by layering several different materials on a silicon base or wafer. The design of an integrated circuit transforms a circuit description into a geometric description, which is known as a layout. A layout includes a set of planar geometric shapes in several layers.
To provide power to the various components, a power mesh is provided. For example, in designs with at least five layers, a power mesh usually lays in the 4
th
and 5
th
layer. If the design of the integrated circuit includes hardmacros, memories and megacells such that power mesh is allowed to run on top of them, various obstacles may be encountered, such as megacells, pins, routing blocks and the like. Because of these obstacles, an equidistant power mesh typically cannot be provided, and the designer has to solve conflicts manually.
Therefore, it would be desirable to provide a system and method for providing a power mesh in an efficient manner.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a system and method for providing a power mesh for an integrated circuit in an efficient manner.
In a first aspect of the present invention, a method for determining strap location in an integrated circuit for power routing includes receiving input parameters for strap placement, the input parameters including 1 through N number of straps, wherein a strap of the number of straps is denoted as i. A middle point for a strap i located between a first strap i+1 and a second strap i−1 is calculated, wherein if the middle point is feasible, the calculated middle point is utilized as a location for strap i.
In a second aspect of the present invention, a method for determining strap location for power routing in an integrated circuit includes receiving input parameters, the input parameters including a number N indicating a number of straps to be located, wherein a strap of the number of straps is denoted as i. An initial strap placement is found for 1 through N straps and strap placement is calculated by relocating a strap if an obstacle is encountered in an initial strap placement, the relocated strap utilized to relocate at least one other strap of the 1 through N straps. Strap placement may be calculated by employing a local gradient method, dynamic programming, and like methods as contemplated by a person of ordinary skill in the art without departing from the spirit and scope thereof.
In a third aspect of the present invention, a system suitable for determining power routing in an integrated circuit without user intervention from received parameters includes a memory suitable for performing a program of instructions and a processor communicatively coupled to the memory, wherein the program of instruction configures the processor to receive input parameters, the input parameters including a number N indicating a number of straps to be located, wherein a strap of the number of straps is denoted as i. An initial strap placement is found for 1 through N straps and strap placement is calculated by relocating a strap if an obstacle is encountered in an initial strap placement, the relocated strap utilized to relocate at least one other strap of the 1 through N straps.
It is to be understood that both the forgoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.
REFERENCES:
patent: 5598348 (1997-01-01), Rusu et al.
patent: 5808900 (1998-09-01), Buer et al.
patent: 5977574 (1999-11-01), Schmitt et al.
patent: 6308307 (2001-10-01), Cano et al.
patent: 6321371 (2001-11-01), Yount, Jr.
Andreev Alexandre E.
Ivanovic Lav D.
Pavisic Ivan
LSI Logic Corporation
Siek Vuthe
Suiter - West PC LLO
Tat Binh C
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