Power reduction method and apparatus for phase-locked loop based

Details Power reduction method and apparatus for phase-locked loop based Power reduction method and apparatus for phase-locked loop based

1996-05-28

1998-04-21

Kuntz, Curtis

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375373, 455260, 455343, H04L 2534, H04L 2549, H04B 106, H04B 116

Patent

active

057426503

ABSTRACT:
A method and apparatus for reducing power associated with acquiring phase-lock between a reference clock signal and an internal clock signal after each exit from a quiescent state by a data processing system. A phase-locked loop (PLL) phase-locks the internal clock signal to the reference clock signal. A set of clock drivers receive an oscillator signal from the PLL and generate a plurality of multi-phase internal clock signals in response thereto. The clock state machine receives a first control signal from the PLL, indicating that the phase-locked loop is re-acquiring phase-lock as a result of the data processing system leaving a quiescent state. The clock state machine suppresses a set of clock state signals to prevent the clock drivers from changing state during the period of time when the phase-locked loop is re-acquiring phase-lock. The invention reduces power consumption associated with acquiring phase-lock by eliminating the power resulting from toggling the clock drivers during each exit from the quiescent state by the data processing system.

REFERENCES:
patent: 4841551 (1989-06-01), Avaneas
patent: 5103192 (1992-04-01), Sekine
patent: 5307381 (1994-04-01), Ahuja
patent: 5371764 (1994-12-01), Gillingham
patent: 5394443 (1995-02-01), Byers
patent: 5544203 (1996-08-01), Casasanta

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