Power reduction for UART applications in standby mode

Pulse or digital communications – Transceivers – Transmission interface between two stations or terminals

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Details

375377, 395560, 39575004, 39575005, 39575006, 455574, 331187, 365227, 327143, 327211, 327544, G06F1/32

Patent

active

059036010

ABSTRACT:
A power reduction system for a UART system having a controllable oscillator for producing free-running clock signals. A controlled clock synchronizer having an output terminal is coupled to the oscillator and responsive to both a first control signal thereto and application of the free-running clock signals thereto to provide synchronized pulses and is responsive to both a second control signal different from the first control signal thereto and application of the free-running clock signals thereto to cease production of the synchronized pulses at the output terminal. A UART core controls the oscillator and the clock synchronizer and is operated under control of clock signals from the clock synchronizer. The controllable oscillator includes an inverter having a feedback circuit thereacross including a switch responsive to the third control signal to cause the oscillator to cease oscillation. The synchronizer includes a bistable circuit responsive to the first and second control signals and a gate responsive to the bistable circuit and the clock signals for controlling the status of the synchronized pulses at the output terminal.

REFERENCES:
patent: 5150081 (1992-09-01), Goldberg
patent: 5568100 (1996-10-01), Locanthi
patent: 5628020 (1997-05-01), O'Brien
patent: 5661751 (1997-08-01), Johnson

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