Electrical computers and digital processing systems: support – Computer power control – Having power source monitoring
Reexamination Certificate
1998-12-15
2001-02-27
Beausoleil, Robert (Department: 2181)
Electrical computers and digital processing systems: support
Computer power control
Having power source monitoring
C713S330000, C702S060000
Reexamination Certificate
active
06195756
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates to microprocessors, and more particularly to methods of using programming instructions in a manner that reduces the power consumption of a processor.
BACKGROUND OF THE INVENTION
Power efficiency for processor-based equipment is becoming increasingly important as people are becoming more attuned to energy conservation issues. Specific considerations are the reduction of thermal effects and operating costs. Also, apart from energy conservation, power efficiency is a concern for battery-operated processor-based equipment, where it is desired to minimize battery size so that the equipment can be made small and lightweight. The “processor-based equipment” can be either equipment designed especially for general computing or equipment having an embedded processor.
From the standpoint of processor design, a number of techniques have been used to reduce power usage. These techniques can be grouped as two basic strategies. First, the processor's circuitry can be designed to use less power. Second, the processor can be designed in a manner that permits power usage to be managed.
On the other hand, given a particular processor design, its programming can be optimized for reduced power consumption. Thus, from a programmer's standpoint, there is often more than one way to program a processor to perform the same function. For example, algorithms written in high level programming languages can be optimized for efficiency in terms of time and power. Until recently, at the assembly language level, most optimization techniques have been primarily focussed on speed of execution without particular regard to power use.
The programmer's task of providing power efficient code can be performed manually or with the aid of an automated code analysis tool. Such a tool might analyze a given program so to provide the programmer with information about its power usage information. Other such tools might actually assist the programmer in generating optimized code.
U.S. Pat. No. 5,557,557, to Franz, et al., entitled “Processor Power Profiler”, assigned to Texas Instruments Incorporated, describes a method of modeling power usage during program execution. A power profiler program analyzes the program and provides the programmer with information about energy consumption. A power profiler is also described in U.S. patent Ser. No. 06/046,811, to L. Hurd, entitled “Module-Configurable, Full-Chip Power Profiler”, now U.S. Pat. No. 6,125,334 assigned to Texas Instruments Incorporated.
Once the power requirements of a particular program are understood, the code can be optimized. Automating this aspect of programming requires a code generation tool that can restructure computer code, internal algorithms as well as supporting functions, for minimum power usage.
SUMMARY OF THE INVENTION
One aspect of the invention is a method of optimizing computer programs for power usage. It is based on the recognition that power consumption is reduced when there is a minimum of change in the machine-level representation of the program from each CPU cycle to the next. The method is useful for various types of processors that execute “multiple-instruction words” (as defined herein) by different functional units of the processor. Examples of such processors are VLIW (very long instruction word) processors and dual datapath processors.
The method comprises a set of steps, any of one which may be performed independently. Each step involves scanning the code and comparing a given field or other code sequence within instructions. Generally, it is the code syntax that is of interest, as opposed to its functionality. It is determined if there are code sequences where cycle-to-cycle bit changes in the machine code representation of that code sequence can be minimized. Then, the code is modified if this can be done without adversely affecting code functionality.
For example, one aspect of the invention is a method where the code sequences of interest are functional unit assignments. Typically, each instruction of the instruction word occupies a “slot” of the word. For each slot, the field that identifies the functional unit is scanned. Cycle-to-cycle bit changes in this field are reduced by re-arranging instructions within instruction words. Because instructions are merely re-arranged, code functionality is not affected.
An advantage of the invention is that it is directed to optimization at the processor architecture level, rather than to high level programming. This permits a processor to be programmed in a manner that is most efficient for that processor. The method can be easily adapted to the characteristics of the processor and its instruction set.
REFERENCES:
patent: 5394558 (1995-02-01), Arakawa et al.
patent: 5495617 (1996-02-01), Yamada
patent: 5557557 (1996-09-01), Frantz et al.
patent: 5584031 (1996-12-01), Burch et al.
patent: 5630130 (1997-05-01), Perotto et al.
patent: 5941991 (1999-08-01), Kageshima
patent: 6002878 (1999-12-01), Gehman et al.
patent: 6125334 (2000-09-01), Hurd
Beausoleil Robert
Brady III W. James
Marshall, Jr. Robert D.
Phan Raymond N
Telecky , Jr. Frederick J.
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