Power reduction circuit and method with multi clock branch...

Details Power reduction circuit and method with multi clock branch... Power reduction circuit and method with multi clock branch...

2005-01-25

2005-01-25

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S501000

Reexamination Certificate

active

06848058

ABSTRACT:
A power consumption reduction circuit and method utilizes a memory clock source and a memory clock divider circuit that generates divided memory clock output signals as a plurality of corresponding independent clock signals to a number of different processing engines. A memory clock divider circuit and method selectively activates a plurality of independent clock signals in response to received condition data. In one embodiment, an engine clock source is also coupled through a switching circuit such that it is selectively output to one or more processing engines. The switching circuit disables the output from the engine clock based on register condition data. In another embodiment, a plurality of memory read latch circuits are controlled by a memory read latch control circuit. The memory read latch control circuit is operative to dynamically activate and deactivate the plurality of memory read latches based on detected memory read requests to facilitate memory access activity-based power reduction.

REFERENCES:
patent: 5544101 (1996-08-01), Houston
patent: 5675808 (1997-10-01), Gulick et al.
patent: 5781768 (1998-07-01), Jones, Jr.
patent: 6256743 (2001-07-01), Lin
patent: 6263448 (2001-07-01), Tsern et al.
patent: 6307281 (2001-10-01), Houston

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