Power rail ESD protection circuit

Details Power rail ESD protection circuit Power rail ESD protection circuit

1991-05-28

1993-08-17

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

361 56, 361 58, 361 91, 361111, 257360, 257363, 257369, H01L 2978

Patent

active

052373959

ABSTRACT:
An electrostatic discharge (ESD) protection circuit for protecting internal devices of an integrated circuit is coupled between the power rails of the integrated circuit. First and second current shunt paths between the power rails are maintained non-conductive during normal circuit operation and are triggered to a conductive mode in response to an ESD event on the power rails. A triggering circuit may employ a logic gate, such as an inverter with its input coupled to the positive power rail, which maintains a low level output during normal operation and provides a high output in response to an ESD event on the power rail.

REFERENCES:
patent: 4990802 (1991-02-01), Smooha
patent: 5021853 (1991-06-01), Mistry
patent: 5051860 (1991-09-01), Lee et al.
L. Avery, "Electrostatic Discharge: Mechanisms, Protection Techniques, and Effects on Integrated Circuit Reliability", RCA Laboratories, Princeton, N.J., Jun. 1983, pp. 291-302.
C. Duvvury, et al., "Internal Chip ESD Phenomena Beyond the Protection Circuit", 1988 IEEE/IRPS, pp. 19-25.
A. Ochoa, et al., "Snap-Back: A Stable Regenerative Breakdown Mode of MOS Devices", IEEE Transactions on Nuclear Science, vol. NS-30, No. 6, Dec., 1983, pp. 4127-4130.

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