Power-optimizing memory analyzer, method of operating the...

Electrical computers and digital processing systems: support – Computer power control

Reexamination Certificate

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Details

C713S320000, C718S100000, C718S102000, C718S104000

Reexamination Certificate

active

07930565

ABSTRACT:
Embodiments of the present disclosure provide a power-optimizing memory analyzer, a method of operating a power-optimizing memory analyzer and a memory system employing the analyzer or the method. In one embodiment, the power-optimizing memory analyzer is for use with an array of memory blocks and includes a task database configured to provide a parameter set corresponding to each of a set of tasks to be performed in a system. The power-optimizing memory analyzer also includes an allocation module configured to determine offline, a group of memory blocks in the array corresponding to the parameter set for each task and based on providing a power reduction for the array. The power-optimizing memory analyzer further includes a power profiling module configured to generate run-time power profiles of memory power states for each task allowing transparent and dynamic control of the memory power states while maintaining a required quality of service.

REFERENCES:
patent: 5148546 (1992-09-01), Blodgett
patent: 6751739 (2004-06-01), Verdun
patent: 7206960 (2007-04-01), Barr et al.
patent: 7454639 (2008-11-01), Jain et al.
patent: 7539994 (2009-05-01), McAlinden et al.
Gary Nutt, Operating Systems: A Modern Perspective, 2000, Second Ed., Addison-Wesley, pp. 293-298.

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