Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2006-03-30
2011-11-29
Rinehart, Mark (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S036000, C710S100000, C714S746000
Reexamination Certificate
active
08069294
ABSTRACT:
A method, apparatus, and system to synchronize multiple host controllers with non-uniform frame rates. The apparatus includes a first host controller, a second host controller, and logic. The first host controller is configured to access memory at a first frame rate. The second host controller is configured to access the memory at a second frame rate which is different from the first frame rate. The logic is coupled to the first and second host controllers to synchronize the memory accesses of the first and second host controllers at a common frame rate. Other embodiments are described.
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Abramson Darren L.
Derr Michael N.
Doucette Bryan C.
Vadivelu Karthi R.
Blakely , Sokoloff, Taylor & Zafman LLP
Daley Christopher A
Intel Corporation
Rinehart Mark
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