Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1998-12-21
2001-03-20
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S198000
Reexamination Certificate
active
06204703
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuits and, more particularly to a power on reset circuit to set logic elements at a desired initialization condition during power-up.
BACKGROUND OF THE INVENTION
In certain integrated circuit (IC) design applications, it is desirable or even necessary to provide a reset signal for certain types of logic elements. These logic elements are typically memory circuits of one type or another which will remain in a certain state once having been set to that state. Such elements include flip-flops, counters, timers and other similar circuits. To ensure proper operation of the circuit which contains such elements, a reset signal is typically provided during power-up of the circuit to set these elements to a certain desired condition. Normally, it is desirable to have this reset occur automatically during power-up, that is, during the period of time when the voltage from the power supply voltage is transitioning from zero volts to the nominal voltage used to power the circuit.
Referring to
FIG. 1
, a power on reset circuit
10
according to the prior art is illustrated. The power on reset circuit
10
is composed of three PMOS transistors
12
,
14
and
20
, three NMOS transistors
16
,
18
and
22
, and one inverter
24
. The PMOS transistor
12
has a source connected to a power supply voltage Vcc, and a drain and a gate of the PMOS transistor
12
are connected both to each other and to a node N
1
. The PMOS transistor
14
, whose gate is connected to a ground voltage Vss, has a source connected to the power supply voltage Vcc and a drain tied to a node N
2
. A gate of the NMOS transistor
16
is coupled to the node N
1
, a drain thereof is connected to the node N
2
, and its source is grounded. The PMOS transistor
20
and the NMOS transistor
22
act as an inverter circuit. Gates of the transistors
20
and
22
are connected in common to the node N
2
and their current paths are sequentially made between the power supply voltage Vcc and the ground voltage Vss. The inverter
24
is connected between the node N
3
and an output terminal
26
for outputting a power on reset signal POR. The NMOS transistor
18
has a gate connected to the output terminal
26
via inverter
24
and a current path made between the node N
2
and the ground voltage Vss.
FIG. 2
shows each waveform at respective nodes N
2
and N
3
and the output terminal
26
during power-up. Operation of the power on reset circuit
10
according to the prior art will be described below with reference to
FIGS. 1 and 2
.
Initially, all transistors of the power on reset circuit
10
are turned off, because no power supply voltage Vcc is present. When the power supply voltage Vcc slowly increases towards a positive value, the PMOS transistor
14
is slightly turned on at a point of time t1. Then, when the power supply voltage Vcc reaches a voltage Va in
FIG. 2
, the PMOS transistor
14
becomes fully conductive, so that the node N
2
is pulled up to the power supply voltage Vcc through the PMOS transistor
14
at a point of time t2, as shown in FIG.
2
.
When the power supply voltage Vcc increases further, the node N
2
, because the PMOS transistor
14
is conducting, will follow the power supply voltage Vcc until the power supply voltage Vcc reaches a voltage Vb in FIG.
2
. At the same time, the PMOS transistor
12
becomes turned on at the same period of time as the PMOS transistor
14
. Therefore, the node N
1
directly follows the power supply voltage Vcc with a voltage difference which corresponds to the magnitude of the threshold voltage of the PMOS transistor
12
.
As the power supply voltage Vcc continues to increase, at a point of time t3, node N
1
reaches a voltage Vb which corresponds to the threshold voltage of the NMOS transistor
16
, enabling the NMOS transistor
16
to become conductive. As shown in
FIG. 2
, the node N
2
does not follow the power supply voltage Vcc any longer, that is, the voltage of the node N
2
is pulled down towards the ground voltage, Vss, through the turned-on NMOS transistor
16
after the point of time t3. The node N
3
goes to a logical high level, that is, the power supply voltage Vcc, through the PMOS transistor
20
, as illustrated in FIG.
2
.
According to the above mentioned process, the power on reset signal POR is first 0 volts since the power supply voltage Vcc is also 0 volts. When the node N
2
follows the power supply voltage Vcc, the node N
3
is at the ground voltage Vss through the NMOS transistor
22
, so that the power on reset signal POR follows the power supply voltage Vcc through the inverter
24
. At this time, the logic elements are initialized to a desired condition by means of the power on reset signal POR having the power supply voltage Vcc, a logical high level. Then, when the node N
2
becomes discharged towards the ground voltage Vss through the NMOS transistor
16
, the power on reset signal POR goes to 0 volts through the inverter
24
. That is, the initialization operation for the logic elements has been completed.
If, however, owing to certain causes the power supply voltage Vcc oscillates around the voltage Vb at a point of time t3 when the power on reset signal POR transitions from the power supply voltage Vcc to the ground voltage Vss, the power on reset signal POR also oscillates. This makes the logic elements perform needless operations. Accordingly, it is one problem of the prior art that the power on reset circuit
10
according to the prior art is easily affected by power noise, for example, a power oscillation phenomenon, during power-up.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a power on reset circuit with improved power noise immunity.
In order to attain the above objects, according to one aspect of the present invention, there is provided a power on reset circuit generating a power on reset signal to set logic elements to a desired initialization state during power-up. The circuit comprises a latch circuit having first and second input terminals and an output terminal for outputting the power on reset signal, and a latch controller connected to the first and second input terminals and having a first threshold voltage and a second threshold voltage higher than the first threshold voltage. The latch controller sets the latch circuit to an initialization state when the power supply voltage is less than the first threshold voltage during power-up, so that the power on reset signal goes to a logically activated state, following the power supply voltage. The latch controller resets the latch circuit when the power supply voltage is higher than the second threshold voltage so that the power on reset signal goes to a logically inactivated state, having the ground voltage level.
REFERENCES:
patent: 5831460 (1998-11-01), Zhou
patent: 5933036 (1998-11-01), Kim
Jones Volentine, L.L.C.
Nguyen Hiep
Samsung Electronics Co,. Ltd.
Tran Toan
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