Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Utility Patent
1997-09-11
2001-01-02
Le, Dieu-Minh T. (Department: 2785)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C713S340000
Utility Patent
active
06170066
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to electronic systems utilizing flash electrically-erasable programmable read-only memory (EEPROM) and, more particularly, to methods and apparatus for managing data in such systems to reduce data loss in case of a power interruption.
2. History of the Prior Art
Recently, flash EEPROM storage devices have been used in arrays as a new form of memory array. A flash EEPROM memory array is constructed of a large plurality of floating-gate metal-oxide-silicon field effect transistor devices arranged as memory cells in typical row and column fashion with circuitry for accessing individual cells and placing the memory transistors of those cells in different memory conditions. Such memory transistors may be programmed by storing a charge on the floating gate. This charge remains when power is removed from the array. This charge (typically called a “zero” or programmed condition) or its absence (a “one” or erased condition) may be detected when the memory cell is read.
These flash memory arrays may be designed to accomplish many of the operations previously accomplished by other forms of memory in digital systems and especially in computer and control systems. For example, flash memory is being used to replace various read-only memories such as the basic input/output startup (BIOS) memory of a computer system. The ability to program flash memory in place offers substantial advantages for BIOS and similar read only memories over more conventional EPROM memory. Because of this ability, its great insensibility to mechanical shock, and its very high reliability, flash memory is also being used in embedded systems to store data generated by operations of associated systems. More recently, flash memory has been used to provide a smaller lighter functional equivalent of an electromechanical hard disk drive. Flash memory is useful for this purpose because it may be read more rapidly and is not as sensitive to physical damage as an electromechanical hard disk drive. Flash drive memories are especially useful in portable devices where space is at a premium and weight is extremely important.
In general, a flash EEPROM memory array is divided into blocks which are connected so that each entire block of memory cells may be erased simultaneously. An erasure places all of the memory cells in the block into the erased condition. Thereafter, a memory cell may be individually programmed to store data. Since all of the memory transistors of a block of the array are joined so that they may be erased together, a cell in a programmed condition cannot be switched to the erased state until the entire block of the array is erased. Contrasted to other memories in which changed data is written, essentially instantaneously, directly in place of the data it replaces, a flash EEPROM memory array requires a time consuming erasure process. Because flash memory is erased in blocks, out-of-date information cannot be erased without erasing all of the valid information that remains in the block along with the invalid information. Consequently, when the information at a data entry changes in flash memory used to store changing information, the new information is written to a new memory area rather than written over the old data; and the old data is marked as invalid. Then, after a sufficient portion of a block has been marked invalid, all valid information remaining in the block is written to the new memory area; and the entire block may then be erased, typically using a background process.
Since the processes by which data is written to and erased from a flash memory array are quite complicated, these processes require significant periods to accomplish. During these periods, it is possible for a system which uses such a flash memory array to lose power. If a system loses power during a write operation which updates data already stored, for example, there is a significant possibility that data will be lost. This is particularly true in embedded systems which utilize flash memory arrays. Embedded systems try to utilize as much of the flash memory as possible for accomplishing their prime purposes and consequently provide minimal data management facilities. In some flash memories, especially those used in embedded systems, a power loss may cause the entire disk to be corrupted and all of the data lost.
It is desirable to provide a low overhead system and apparatus for managing the write and erase processes of flash memory arrays in order to obviate the problems which bring about a significant loss of data.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide improved low overhead apparatus and a method for managing flash memory to obviate the loss of data and formatting during power losses.
This and other objects of the present invention are realized by a method of managing data in a flash EEPROM memory array so that all data can be recovered after power loss except the new data in a sector in which the data content is being changed when power is lost, the method including providing a block data structure and a plurality of sector data structures in each block of a flash EEPROM memory array, each data structure storing an indication of the operating state of the block or an associated physical sector of the array; changing the indication stored in the block data structure or the sector data structure when the operating state of the block or of the associated sector changes; detecting the indication stored in the block data structure and the sector data structures when power is restored to a system which has lost power; and managing the flash EEPROM memory array depending on the indications detected.
These and other objects and features of the invention will be better understood by reference to the detailed description which follows taken together with the drawings in which like elements are referred to by like designations throughout the several views.
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Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Le Dieu-Minh T.
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