Power network synthesizer for an integrated circuit design

Details Power network synthesizer for an integrated circuit design Power network synthesizer for an integrated circuit design

2008-04-01

2008-04-01

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07353490

ABSTRACT:
A plan for a power network for an integrated circuit device is automatically preparing in two stages. In a first stage, a number of simplified plans are prepared on a global scale, without regard to design rule checking constraints and routing blockages. Next, the simplified plans are evaluated to select a plan that conforms to a user-specified limit for an attribute, such as maximum voltage drop. The selected simplified plan, which identifies a total count of power wires and a width of the power wires, is used in a second stage to prepare a more detailed plan that honors the design rule checking constraints and routing blockages. The detailed plan is evaluated to check for conformance with the user-specified limit on the attribute, and if necessary the detailed plan is changed, e.g. by increasing wire width one or more times, to achieve conformance.

REFERENCES:
patent: 4726991 (1988-02-01), Hyatt et al.
patent: 4811237 (1989-03-01), Putatunda et al.
patent: 5598348 (1997-01-01), Rusu et al.
patent: 5808900 (1998-09-01), Buer et al.
patent: 5933358 (1999-08-01), Koh et al.
patent: 6043672 (2000-03-01), Sugasawara
patent: 6202191 (2001-03-01), Filippi et al.
patent: 6202196 (2001-03-01), Huang et al.
patent: 6308307 (2001-10-01), Cano et al.
patent: 6311147 (2001-10-01), Tuan et al.
patent: 6405357 (2002-06-01), Chao et al.
patent: 6446245 (2002-09-01), Xing et al.
patent: 6457157 (2002-09-01), Singh et al.
patent: 6487706 (2002-11-01), Barkley et al.
patent: 6510539 (2003-01-01), Deemie et al.
patent: 6523154 (2003-02-01), Cohn et al.
patent: 6598206 (2003-07-01), Darden et al.
patent: 6675139 (2004-01-01), Jetton et al.
patent: 6981230 (2005-12-01), Lin et al.
patent: 6991961 (2006-01-01), Hubbard et al.
patent: 7043389 (2006-05-01), Plusquellic
patent: 7111265 (2006-09-01), Tan et al.
patent: 2001/0039642 (2001-11-01), Anzai
patent: 2002/0013931 (2002-01-01), Cano et al.
patent: 2002/0170020 (2002-11-01), Darden et al.
patent: 2003/0140327 (2003-07-01), Lai et al.
patent: 2003/0151047 (2003-08-01), Corbett et al.
patent: 2003/0237059 (2003-12-01), Sclrultz
patent: 2004/0088443 (2004-05-01), Tran et al.
patent: 2004/0163054 (2004-08-01), Frank et al.
patent: 2004/0268281 (2004-12-01), Dotson et al.
patent: 2005/0050502 (2005-03-01), Kurihara et al.
patent: 2005/0090916 (2005-04-01), Aghababazadeh et al.
patent: 2005/0236177 (2005-10-01), Inagaki et al.
patent: 2006/0080630 (2006-04-01), Lin
patent: 2006/0095872 (2006-05-01), McElvain et al.
patent: 2006/0239102 (2006-10-01), Saita et al.
Office Action dated Jul. 27, 2007 in U.S. Appl. No. 10/976,653.
U.S.Appl. No. 10/976,719, filed on Oct. 29, 2004 by Kwon et al.
Office Action dated Feb. 9, 2007 in U.S. Appl. No. 10/976,719.
Amendment dated Jun. 11, 2007 in U.S. Appl. No. 10/976,719.
U.S. Appl. No. 10/976,653, filed on Oct. 29, 2004 by Tai et al.
Office Action dated Jan. 29, 2007 in U.S. Appl. No. 10/976,653.
Amendemnt dated Apr. 30, 2007 in U.S. Appl. No. 10/976,653.
M. Zhao et al., Optimal Placement of Power Supply Pads and Pins, (DAC), pp. 165-170, 2004.
J. Oh et al., “Multi-pad Power/Ground Network Design for Uniform Distribution of Ground Bounce”, (DAC), pp. 287-290, 1998.
S. R. Nassif et al., “Fast Power Grid Simulation”, (DAC), 2000.
H. Su et al., “Analysis and Optimization of Structured Power/Ground Networks”, Department of Electrical and Computer Engineering University of Minnesota, (date believed to be prior to Oct. 2004).
L. T. Pillage et al, “Electronic Circuit and System Simulation Methods”, McGraw-Hill, Inc., 1994.
Gupta et al. “A High Level Interconnect Power Model for Design Space Exploration”, Intnl. Conference on Computer Aided Design, Nov. 9-13, 2003, pp. 551-558.
Chen, H.H. et al., “Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design”, (DAC), 1997, p. 6;.
Nassif, S.R. et al., “Fast Power Grid Simulation”, (DAC), 2000, p. 6;.
Su, H. et al., “Analysis and Optimization of Structured Power/Ground Networks”, Department of Electrical and Computer Engineering University of Minnesota, (date believed to be prior to Oct. 2004), p. 33;.
Golub, G.H. et al., “Matrix Computations”, 520-537, Third Edition 1996, The Johns Hopkins University Press, p. 20;.
Eisenstat, S.C. et al., “Yale Sparse Matrix Package I: The Symmetric Codes”, International Journal for Numerical Methods in Engineering, vol. 18, 1145-1151 (1982), p. 7;.
Pillage, L.T. et al., “Electronics Circuit and System Simulation Methods”, McGraw-Hill, Inc., 1994, p. 11;.
Bentley, J.L. et al., “Data Structures for Range Searching”, Computer Surveys, vol. 11, No. 4, Dec. 1979, pp. 397-409, p. 13.
Office Action dated Aug. 27, 2007 by Examiner Suchin Parihar in U.S. Appl. No. 10/976,719.
Amendment dated Oct. 29, 2007 in U.S. Appl. 10/976,719;.
Amendment dated Oct. 29, 2007 in U.S. Appl. 10/976,653.
Entire Prosecution History of U.S. Appl. No. 11/930,020, filed on Oct. 30, 2007;.
Entire Prosecution History of U.S. Appl. No. 11/982,094, filed on Oct. 31, 2007;.
Notice of Allowance dated Nov. 30, 2007 in U.S. Appl. No. 10/976,653.

Affiliated with

Also associated with

Rating

Power network synthesizer for an integrated circuit design does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Power network synthesizer for an integrated circuit design, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power network synthesizer for an integrated circuit design will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2770360