Power network analyzer for an integrated circuit design

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000

Reexamination Certificate

active

10976653

ABSTRACT:
A design of an integrated circuit device, in which locations of power wires and memory/logic circuitry are known, is analyzed by at least: identifying intersections of power wires with one another, for power wires that are electrically connected to one another through vias; segmenting power wires, at their intersections; preparing estimates of conductance of vias and wire segments in the form of conductance matrix G; and preparing estimates of current I at each intersection based on power consumed by surrounding circuitry, and current vector “I” and conductance matrix “G” are used to solve for voltage drop ΔV, in a matrix equation GΔV=I, and the voltage drop is displayed, to allow a human to make changes in the design. Pins of unconnected hard macros are temporarily connected to their closest wires, and current therethrough is included in the estimates.

REFERENCES:
patent: 4726991 (1988-02-01), Hyatt et al.
patent: 4811237 (1989-03-01), Putatunda et al.
patent: 5598348 (1997-01-01), Rusu et al.
patent: 5808900 (1998-09-01), Buer et al.
patent: 5933358 (1999-08-01), Koh et al.
patent: 6043672 (2000-03-01), Sugasawara
patent: 6202191 (2001-03-01), Filippi et al.
patent: 6202196 (2001-03-01), Huang et al.
patent: 6308307 (2001-10-01), Cano et al.
patent: 6311147 (2001-10-01), Tuan et al.
patent: 6405357 (2002-06-01), Chao et al.
patent: 6446245 (2002-09-01), Xing et al.
patent: 6457157 (2002-09-01), Singh et al.
patent: 6487706 (2002-11-01), Barkley et al.
patent: 6510539 (2003-01-01), Deemie et al.
patent: 6523154 (2003-02-01), Cohn et al.
patent: 6598206 (2003-07-01), Darden et al.
patent: 6675139 (2004-01-01), Jetton et al.
patent: 6981230 (2005-12-01), Lin et al.
patent: 6991961 (2006-01-01), Hubbard et al.
patent: 7043389 (2006-05-01), Plusquellic
patent: 7111265 (2006-09-01), Tan et al.
patent: 2001/0039642 (2001-11-01), Anzai
patent: 2002/0013931 (2002-01-01), Cano et al.
patent: 2002/0170020 (2002-11-01), Darden et al.
patent: 2003/0140327 (2003-07-01), Lai et al.
patent: 2003/0151047 (2003-08-01), Corbett et al.
patent: 2003/0237059 (2003-12-01), Schultz
patent: 2004/0088443 (2004-05-01), Tran et al.
patent: 2004/0163054 (2004-08-01), Frank et al.
patent: 2004/0268281 (2004-12-01), Dotson et al.
patent: 2005/0050502 (2005-03-01), Kurihara et al.
patent: 2005/0090916 (2005-04-01), Aghababazadeh et al.
patent: 2006/0080630 (2006-04-01), Lin
patent: 2006/0095872 (2006-05-01), McElvain et al.
patent: 2006/0239102 (2006-10-01), Saita et al.
Gupta et al., “A High-Level Interconnect Power Model for Design Space Exploration”, International Conference on Computer Aided Design, Nov. 9-13, 2003, pp. 551-558.
G. H. Golub et al., “Matrix Computations”, Third Edition 1996, The Johns Hopkins University Press, pp. 520-537.
S. C. Eisenstat et al., “Yale Sparse Matrix Package I: The Symmetric Codes”, International Journal For Numerical Methods in Engineering, vol. 18, pp. 1145-1151, 1982.
L. T. Pillage et al., “Electronic Circuit and System Simulation Methods”, McGraw-Hill, Inc., 1994, pp. 1-17.
J. L. Bentley et al., “Data Structures for Range Searching”, Computer Surveys, vol. 11, No. 4, Dec. 1979, pp. 397-409.
Entire Prosecution History of U.S. Appl. No. 11/930,020, filed on Oct. 30, 2007.
Entire Prosecution History of U.S. Appl. No. 11/982,094, filed on Oct. 31, 2007.
Notice of Allowance dated Oct. 22, 2007 in U.S. Appl. No. 10/976,411.
Amendment dated Oct. 29, 2007 in U.S. Appl. No. 10/976,719.
Office Action dated Feb. 9, 2007 by Examiner Suchin Parihar in U.S. Appl. No. 10/976,719.
Amendment dated Jun. 11, 2007 in U.S. Appl. No. 10/976,719.
Office Action dated Jul. 3, 2006 by Examiner Thuan Do in U.S. Appl. No. 10/976,411.
Amendment dated Nov. 3, 2006 in U.S. Appl. No. 10/976,411.
Office Action dated Jan. 18, 2007 by Examiner Thuan Do in U.S. Appl. No. 10/976,411.
Interview Summary dated May 10, 2007 in U.S. Appl. No. 10/976,411.
Office Action dated May 1, 2007 by Examiner Thuan Do in U.S. Appl. No. 10/976,411.
Amendment dated Sep. 4, 2007 in U.S. Appl. No. 10/976,411.
Entire Prosecution History of U.S. Appl. No. 10/976,411, including all Office Actions and Amendments.
Entire Prosecution History of U.S. Appl. No. 10/976,719 including all Office Actions and Amendments.
M. Zhao et al., Optimal Placement of Power Supply Pads and Pins, (DAC), pp. 165-170, 2004.
J. Oh et al., “Multi-pad Power/Ground Network Design for Uniform Distribution of Ground Bounce”, (DAC), pp. 287-290, 1998.
H. H. Chen et al., “Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design”, (DAC), pp. 1-6, 1997.
S. R. Nassif et al., “Fast Power Grid Simulation”, (DAC), pp. 1-6, 2000.
H. Su et al., “Analysis and Optimization of Structured Power/Ground Networks”, Department of Electrical and Computer Engineering University of Minnesota, pp. 1-33, (date believed to be prior to Oct. 2004).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Power network analyzer for an integrated circuit design does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Power network analyzer for an integrated circuit design, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power network analyzer for an integrated circuit design will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3921348

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.