Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-27
2002-10-08
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S341000
Reexamination Certificate
active
06462378
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power semiconductor device, and more particularly, to a power MOS transistor with decreased body resistance under a source region.
2. Description of the Related Art
A typical power metal oxide semiconductor (MOS) transistor is more advantageous than a bipolar transistor. For instance, the input impedance of a MOS transistor is high, so that it has a high power gain and its gate driving circuit is very simple. Furthermore, the MOS transistor is a unipolar device, so that no time delay occurs due to accumulation or re-combination by source carriers during turn-off. Thus, the power MOS transistor is widely used in switching mode power supplies, lamp ballasts and a motor drive circuits. A double diffused MOS (DMOS) structure using planar diffusion technology is used as the power MOS transistor in such devices.
FIG. 1
is a layout of a typical vertical DMOS transistor.
Referring to
FIG. 1
, a source contact
30
is formed inside a loop formed by gate electrode
19
on a semiconductor substrate (not shown), and a multiplicity of drain contacts
40
are formed outside the gate electrode
19
. A p-type body region
14
is formed in the substrate, such that it is overlapped by the gate electrode
19
. An n-type source region loop
15
that is heavily doped and has a predetermined width d is formed in the p-type body region
14
. A p-type heavily-doped region
16
is formed inside the n-type source region loop
15
. An n-type heavily-doped drain region
18
is formed under the drain contacts
40
. The n-type heavily doped drain region
18
is completely surrounded with an n-type heavily-doped sink region
17
.
FIG. 2
is a sectional view of the vertical DMOS transistor taken along the line I—I of FIG.
1
.
Referring to
FIG. 2
, an n-type heavily-doped buried layer
11
is formed on a semiconductor substrate
10
and an n-type lightly-doped epitaxial layer
12
is formed on the n-type heavily-doped buried layer
11
. An n-type well region
13
is formed in a region of the top of the n-type lightly-doped epitaxial layer
12
, and a p-type body region
14
is formed in a predetermined region of the top of the n-type well region
13
. An n-type heavily-doped sink region
17
is formed in another region of the n-type well region
13
, and the bottom of the n-type heavily-doped sink region
17
overlaps with a region of the top of the n-type heavily doped buried layer
11
. A multiplicity of n-type source region loops
15
, spaced apart by a predetermined interval, are formed in the p-type body region
14
, and the p-type heavily-doped region
16
is formed between the n-type source region loop
15
. Also, an n-type heavily-doped drain region
18
is formed in the top of the n-type heavily-doped sink region
17
. Meanwhile, parts of the n-type source region loop
15
and the p-type heavily-doped region
16
directly contact a source electrode
21
, and the n-type heavily-doped drain region
18
directly contacts a drain electrode
22
. The gate electrode
19
is connected to both the n-type source region loop
15
and part of the p-type body region
14
through a gate insulating layer
20
so that a conductive channel is formed under predetermined conditions. The gate, drain, and source electrodes, respectively
19
,
21
, and
22
, are insulated from each other by an insulating layer
23
, and an active region is defined by a field oxide layer
24
.
When the device operates with a large current and has a low ruggedness, the amount of reverse current is increased, so that turn-on of a parasitic bipolar transistor occurs.
In particular, a large reverse current passes through the p-type body region
14
near the bottom of the n-type source region loops
15
during a reverse recovery operation of switching and passes to the source electrode
21
via the p-type heavily-doped region
16
. However, a predetermined resistance component (p-type body resistance component) exists in the p-type body region,
14
of the bottom of the n-type source region loop
15
, and a voltage drop occurs due to the reverse current passing through the resistance component. When the voltage drop is large enough to forward-bias a pn junction formed by the p-type body region
14
and the n-type source region loop
15
, a parasitic npn bipolar transistor is turned on so that a large amount of current flows from the n-type source region loop
15
to the n-type well region
13
. Thus, the device cannot be controlled by the gate voltage, and the device itself may be damaged due to excessive current.
The phenomenon of turn-on of the parasitic bipolar transistor can be suppressed in various ways, typically by reducing the p-type body resistance.
FIG. 3
is a sectional view of a conventional vertical DMOS transistor in which the p-type body resistance is reduced. The same reference numerals as those of
FIG. 2
represent the same elements.
As shown in
FIG. 3
, a p-type heavily-doped region
50
is formed in the p-type body region
14
. Thus, the p-type body resistance is lowered, so that the voltage drop due to reverse current is reduced to suppress the turn-on of the parasitic bipolar transistor. But, an additional mask layer is required for forming the p-type heavily-doped region
50
, thereby complicating the manufacturing processes.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a power MOS transistor in which the structure of a source region is changed to suppress turn-on of a parasitic bipolar transistor by reducing the body resistance under the source region.
To achieve the above object, according to the power MOS transistor of the present invention, a drift region of a first conductivity type is formed on a semiconductor substrate, and a body region of a second conductivity type is formed on a predetermined upper region of the drift region. A source region of the first conductivity type including a first source region loop is formed in the body region, adjacent to a channel formation portion of the body region, and, a second source region facing portions of the first source region. Heavily-doped regions of the second conductivity type are formed between the first source region in the body region and the second source region. A drain region of the first conductivity type is formed in a predetermined region of the drift region. An insulating layer is formed between the first source region and the edge of the body region, and a gate electrode is formed over the insulating layer. A source electrode is formed by a source contact exposing the second source region and the heavily-doped region of the second conductivity type, and a drain electrode is formed by a drain contact exposing the drain region.
Preferably, the second source region is formed in the shape of a cross which intersects at the center of the source contact.
Preferably, the heavily-doped regions of the second conductivity type are symmetrically formed at an edge of source contact.
According to the power MOS transistor of the present invention, as a length of the source region adjacent to the channel is reduced, the resistance value under the source region is reduced during flow of the reverse current, and thus turn-on of the parasitic bipolar transistor is suppressed. Also, the p-type heavily-doped regions are symmetrically formed, so that all resistance values are uniform and thus current uniformly flows. Further, as the p-type heavily-doped region becomes larger, the amount of the reverse current is increased, to thereby increase the ruggedness of the device.
REFERENCES:
patent: 4837606 (1989-06-01), Goodman et al.
patent: 4860072 (1989-08-01), Zommer
patent: 5923065 (1999-07-01), So et al.
patent: 6043532 (2000-03-01), Depetro et al.
patent: 6111278 (2000-08-01), Kim
Abraham Fetsum
Fairchild Korea Semiconductor Ltd.
Rothwell Figg Ernst & Manbeck
LandOfFree
Power MOSFET with decreased body resistance under source region does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Power MOSFET with decreased body resistance under source region, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power MOSFET with decreased body resistance under source region will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2960744