Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-24
2003-12-16
Nadav, Ori (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S341000, C257S401000
Reexamination Certificate
active
06664595
ABSTRACT:
This application relies for priority upon Korean Patent Application No. 99-10512, filed on Mar. 26, 1999, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a power MOS field effect transistor (a power MOSFET) and a manufacturing method thereof. More particularly the present invention relates, to a power MOSFET having a low on-resistance and high ruggedness, and to a manufacturing method thereof.
Compared to a bipolar transistor, a typical power MOSFET has a low input impedance, a high switching speed, and an excellent safe operating region. However, the power MOSFET also includes a parasitic bipolar transistor. When this parasitic bipolar transistor is turned on, a device is latched into the ON-state and thus may be damaged.
There have been various methods proposed for suppressing the turning-on of the parasitic bipolar transistor, and the method of forming an emitter ballast resistance is typical. By this method, the movement of current flowing through a source contact in an n
+
-type source region is lengthened, thus increasing the potential in an n
+
-type source region, and reducing the potential difference across a junction between the n
+
-source region and a p
−
-type body region. This suppresses the turning-on of the parasitic bipolar transistor.
FIG. 1
is a cell layout of a conventional power MOSFET in which an emitter ballast resistance is formed to suppress the turning-on of a parasitic bipolar transistor.
Referring to
FIG. 1
, a gate electrode
10
has a predetermined opening
5
. A p
−
type body region
11
is an inner region indicated by dotted lines, and is formed by ion implantation and diffusion processes using the gate electrode as a mask. An n
+
-type source region
12
includes tetragonal side regions in a predetermined surface region of the p
−
type body region
11
. Also, the n
+
-type source region
12
includes a contact region for connecting the source region
12
with a source electrode.
In this conventional power MOSFET, current partially flows along the side regions of the n
+
-type source region
12
to a source contact
13
via the contact region. Thus, the length of the n
+
-type source region
12
in which current moves is longer than that of the conventional power MOSFET in which all regions of the n
+
-type source region
12
contacts the source electrode, to thereby increase the size of the voltage drop. As a result, the potential difference between the n
+
-type source region
12
and the p
−
type body region
11
is decreased, to suppress the turning-on of a parasitic bipolar transistor.
In the power MOSFET described above, n
+
-type source regions are sequentially formed around the p
−
-type body region
11
, and so parasitic bipolar transistors exist sequentially around the p
−
type body region
11
. As a result, the turning-on of the parasitic bipolar transistor can be suppressed by the emitter ballast resistance, which is limited due to an increase in the density of the parasitic bipolar transistor. Also, the paths in which the current moves in the n
+
-type source region
12
are divided, so that the emitter ballasting effect may be decreased.
To solve the above problems, the integration density of the parasitic bipolar transistor must be reduced. However, this also reduces the density of the channel, which can increase the on-resistance and the size of the device. Thus, there is a trade-off between the ruggedness capable of sufficiently suppressing turn-on of the parasitic bipolar transistor and low on-resistance.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a power MOSFET in which the structures of a body region and a source region are changed to thereby obtain low on-resistance and high ruggedness.
It is another object of the present invention to provide a method for manufacturing a power MOSFET having a low on-resistance and high ruggedness.
Accordingly, to achieve the first object, a power MOSFET that comprises a drain region formed of a semiconductor substrate of a first conductivity type, a drift region formed on the drain region, having the same conductivity type as the drain region, a gate insulating layer on the drift region, having a plurality of openings spaced apart from each other by a predetermined distance, the plurality of openings partially exposing the drift region, a gate electrode formed on the gate insulating layer, a plurality of body regions of a second conductivity type, each body region being formed in the drift region beneath a corresponding opening and having a plurality of side portions overlapped by the gate electrode, wherein at least two first side portions have a channel formed in them, and at least two second side portions do not have a channel formed in them, a plurality of source regions, each source region being formed in a corresponding body region, each source region including a plurality of first source regions each shaped in the form of a strip, each of the plurality of first source regions contacting a first side portion of the corresponding body region, and a second source region connecting the first source regions, a source electrode electrically connected to the source region, and a drain electrode electrically connected to the drain region.
Preferably, the at least two second side portions are not adjacent to each other.
The body region may comprise a plurality of first body regions contacting a surface of the drift region, being overlapped by the gate electrode, and contacting corresponding first source regions thereby form a plurality of channels, a plurality of second body regions contacting the surface of the drift region, being overlapped by the gate electrode, but not contacting any of the first source regions, a third body region contacting the surface of the drift region exposed by the opening, the third body region formed between the plurality of first source regions and directly contacting the plurality of second body regions, and a fourth body region connecting the first and the second source regions, wherein in the drift region, the fourth body region connects the first region, the second region and the third region to each other.
The impurity concentration of the plurality of second body regions and the third body region is preferably higher than that of the plurality of first body regions. Preferably, the plurality of second body regions are each parallel to corresponding second source regions.
The source electrode preferably contacts the second source region through a source contact. Preferably, the opening is tetragonal or hexagonal.
To achieve the second object, a method for manufacturing a power MOSFET is provided. This method comprises forming a drain region using a semiconductor substrate of a first conductivity type, forming a drift region on the drain region, the drift region having the same conductivity type as the drain region, forming a gate insulating layer on the drift region, the gate insulating layer having openings of a polygonal shape that partially expose the drift region, forming a gate electrode on the gate insulating layer, forming a body region of a second conductivity type in the drift region through ion implantation and diffusion processes using the gate electrode as a mask, and extending the body region into the drift region on all sides of the opening such that the gate electrode overlaps sides of the body region, forming a source region of the first conductivity type to form channels in fewer than all of the sides of the body region through ion implantation and diffusion processes using the gate electrode and the mask pattern as a mask, forming a source electrode to be electrically connected to the source region, and forming a drain region to be electrically connected to the drain region.
The mask pattern used for forming the source region preferably includes a first opening contacting at least two facing sides of the opening, spaced a
Kim Tae-hoon
Yun Chong-man
Fairchild Korea Semiconductor Ltd.
Nadav Ori
Volentine & Francos, PLLC
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