Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-01-28
2004-04-13
Lebentritt, Michael S. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S335000, C257S344000
Reexamination Certificate
active
06720618
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-349152, filed Nov. 14, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a power semiconductor device and, more particularly, to a power MOSFET device
2. Description of the Related Art
In recent years, there has been a rapidly increasing demand for power MOSFET devices in a market of large current switching power supply devices with a high breakdown voltage, as well as in the market of switching power supply devices for mobile telecommunications devices including notebook-sized personal computers (PCs) so as to realize highly power-saving. Since power MOSFET devices are adapted to applications particularly in the field of power management circuits and safety circuits for lithium ion cells, they are required to provide a number of functional features including a low voltage drive capability that allows them to be used directly with the cell voltage, a low ON resistance and a reduced switching loss. These functional features can be realized by a reduced capacitance between the gate and the drain of the power MOSFET device. To meet these requirements, studies are made for applying horizontal element structures that have hitherto been mainly used for ICs to discrete elements in addition to the use of vertical element structures. With the use of the horizontal element structure, it is possible to reduce both the ON-resistance and the capacitance between the gate and the drain of a power MOSFET device.
FIG. 79
of the accompanying drawing is a schematic cross sectional view of a conventional vertical type power MOSFET device. With this vertical type power MOSFET device, an n−type epitaxial layer
102
is formed on an n+ type semiconductor substrate
101
and a pair of p-type base layers
103
a
,
103
b
is formed on respective surface regions of the epitaxial layer
102
with a predetermined distance separating them. Then, n+ type source regions
104
a
,
104
b
are formed respectively on surface regions of the p-type base layers
103
a
,
103
b
that are separated from a boundary between the epitaxial layer
102
and the p-type base layers
103
a
,
103
b
by a distance corresponding to the channel length. The n+ type source regions
104
a
,
104
b
are located adjacent to respective p+ type layers
105
a
,
105
b
which are used for connection to a power source. Subsequently, a gate electrode
106
is formed between the pair of source regions
104
a
,
104
b
to cover the surfaces of the base layers
103
a
,
103
b
and all the surface of the epitaxial layer
102
with a gate insulating film
107
interposed between them. Source electrodes
108
a
,
108
b
are formed on the respective surfaces of the p+ type layers
105
a
,
105
b
so as to partly cover the surfaces of the source regions
104
a
,
104
b
. A drain electrode
109
is formed on the lower surface of the n+ type semiconductor substrate
101
.
FIG. 80
is a schematic cross sectional view of another conventional power MOSFET device, wherein a lateral element structure is applied to a discrete element in order to reduce the capacitance between the gate and the drain thereof. Referring to
FIG. 80
, an n− type epitaxial layer
202
is formed on an n+ type semiconductor substrate
201
and a pair of p type base layers
203
a
,
203
b
is formed on respective surface regions of the epitaxial layer
202
with a predetermined distance separating them. Then, n+ type source regions
204
a
,
204
b
are formed respectively on surface regions of the p type base layers
203
a
,
203
b
with a distance separated from a boundary between the epitaxial layer
202
and the base layers
203
a
,
203
b
corresponding to the channel length. The layers
204
a
,
204
b
are located adjacent to respective p+ type layers
205
a
,
205
b
which are used for connection to a power source. N-type LDD layers
207
a
,
207
b
are formed on the surface of the epitaxial layer
202
between the pair of p type base layers
203
a
,
203
b
with a deep n+ type sinker layer
206
interposed between them. The sinker layer
206
is so deep as to get to the n+ type substrate
201
. Then, between the paired source regions
204
a
,
204
b
and the corresponding paired LDD layers
207
a
,
207
b,
gate electrodes
208
a
,
208
b
are formed to cover the surfaces of the base layers
203
a
,
203
b
and those of the epitaxial layer
202
with gate insulating films
209
a
,
209
b
interposed between them respectively. Source electrodes
210
a
,
210
b
are formed respectively on the surfaces of the p+ type layers
205
a
,
205
b
so as to partly cover the surfaces of the source regions
204
a
,
204
b
. A drain electrode
211
is formed on the lower surface of the n+ type substrate
201
.
The conventional vertical type power MOSFET device shown in
FIG. 79
is accompanied by a problem of a large capacitance between the gate and the drain and a slow switching speed because the n− type epitaxial layer
102
and the gate electrode
106
are arranged oppositely over a large area with the gate insulating film
107
interposed between them.
On the other hand, the conventional horizontal type power MOSFET device shown in
FIG. 80
has a problem that any effort for reducing the pitch of arrangement of elements, or the distance between the gate electrodes
208
a
,
208
b
faces the limit because the central sinker layer
206
is formed by diffusion and its surface width expands substantially as large as the distance between the surface and the n+ type substrate
201
. Accordingly, any attempt at reducing the ON-resistance per unit sectional area also faces a limit.
BRIEF SUMMARY OF THE INVENTION
According to one aspect of the present invention, there is provided a power MOSFET device comprising:
a low resistance substrate of the first conductivity type;
a high resistance epitaxial layer of the first conductivity type formed on the low resistance substrate;
a base layer of the second conductivity type formed in a surface region of the high resistance epitaxial layer;
a source region of the first conductivity type formed in a surface region of the base layer;
a gate insulating film formed on the surface of the base layer so as to contact the source region;
a gate electrode formed on the gate insulating film; and
an LDD layer of the first conductivity type formed on the surface of the high resistance epitaxial layer relative to the source region and the gate electrode;
wherein the LDD layer and the low resistance substrate are connected to each other by the high resistance epitaxial layer.
REFERENCES:
patent: 6372557 (2002-04-01), Leong
patent: 6600182 (2003-07-01), Rumennik
patent: 2002/0050619 (2002-05-01), Kawaguchi et al.
patent: 2000-156383 (2000-06-01), None
E. Yanokura,“Switching Power Supply”, Symposium 2001, pp B2-1-1—B2-1-6.
Hodama Shinichi
Kawaguchi Yusuke
Nakagawa Akio
Ono Syotaro
Yasuhara Norio
Lebentritt Michael S.
Smith Brad
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