Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-08-29
2003-05-20
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S401000
Reexamination Certificate
active
06566710
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to power MOSFETs and, more particularly, to a power MOSFET cell with a crossed bar shaped body contact area.
2. Description of the Related Art
A power MOSFET is a high-voltage transistor that conducts large amounts of current when turned on. A lateral double-diffused MOS (LDMOS) transistor is one type of power MOSFET. LDMOS transistors are commonly implemented with a checkerboard pattern of drain and source regions rather than with a single drain region and a single source region. With this type of transistor, adjacent drain and source regions, known as transistor cells, each contribute a portion of the total current output by the transistor.
FIG. 1
shows a plan view that illustrates a conventional checkerboard-patterned, n-channel LDMOS transistor
100
.
FIG. 2
shows a cross-sectional diagram of transistor
100
taken along lines
2
—
2
of
FIG. 1
, while
FIG. 3
shows a cross-sectional diagram of transistor
100
taken along lines
3
—
3
of FIG.
1
.
As shown in
FIGS. 1-3
, transistor
100
, which is formed on a p− semiconductor substrate
110
, includes an n+ buried layer
112
that is formed on substrate
110
, and an n drift layer
114
that is formed on buried layer
112
. Transistor
100
also includes an alternating pattern of n− field regions
116
and p− body regions
118
that are formed in layer
114
.
Further, transistor
100
includes a checkerboard pattern of n+ drain and source regions
120
and
122
, respectively, that are formed in n− regions
116
and p− regions
118
, respectively. Source region
122
can have a variety of shapes including a square shape (as shown in FIG.
1
), a hexagonal shape, and a circular shape. Adjacent drain and source regions
120
and
122
, in turn, define a number of transistor cells
124
.
Thus, as shown in
FIG. 1
, except for the drain regions
120
on the outside edge of the pattern, each drain region
120
is a part of four transistor cells
124
. Similarly, except for the source regions
122
on the outside edge of the pattern, each source region
122
is a part of four transistor cells
124
. As a result, the center source region
122
shown in
FIG. 1
receives current from four drain regions
120
: the drain region directly above the center region, the drain region directly below the center region, the drain region directly left of the center region, and the drain region directly right of the center region.
Transistor
100
additionally includes a number of p+ contact regions
126
that are formed in p− regions
118
adjacent to source region
122
, and a number of n− regions
130
that are formed in p− regions
118
adjacent to source region
122
. Transistor
100
also includes a number of field oxide regions FOX that surround drain regions
120
, and a layer of gate oxide
132
that is formed over a portion of each body region
118
and an adjoining drift region
114
. The field oxide region FOX separates drain region
120
from source region
122
. (Drain region
120
and source region
122
can alternately be separated by a gap.)
Further, a gate
134
is formed between each drain and source region
120
and
122
on gate oxide layer
132
and the adjoining field oxide region FOX. In addition, an oxide spacer
136
is formed adjacent to each gate
134
over n− region
130
. A salicide layer is also formed on each drain region
120
to form drain contacts
138
, source region/contact region
122
/
126
to form source body contacts
140
, and gate
134
to form gate contacts
142
.
In operation, when the junction of drift region
114
and p− body region
118
of a transistor cell
124
is reverse biased, such as when a positive voltage is applied to drain contact
138
and ground is applied to source body contact
140
of the cell, an electric field is established across the junction. The electric field, in turn, forms a depletion region around the junction that is free of mobile charge carriers.
When the voltage on drain contact
138
of the cell is increased, the strength of the electric field is also increased. When the voltage on drain contact
138
exceeds a snapback voltage, mobile charge carriers in the depletion region, such as electrons from thermally-generated, electron-hole pairs, are accelerated under the influence of the electric field into having ionizing collisions with the lattice.
The ionizing collisions, in turn, form more mobile charge carriers which then have more ionizing collisions until, by a process known as avalanche multiplication, a current flows across the junction between drift region
116
and p− body
118
. The holes that flow into p− body region
118
are collected by p+ contact region
126
, while the electrons that flow into drift region
118
are collected by drain region
120
.
As shown in
FIG. 1
, the holes flowing through p− body region
118
to p+ region
126
can follow a number of paths that include a short path
160
that has the shortest length Lp and a long path
162
that has the longest-length Lw (where Lw=Lp*sqrt(2)). For example, if a hole is generated at point A in
FIG. 1
, the shortest path from point A to p+ region
126
is along a line L
1
that includes length Lp.
The holes flowing through p− body region
118
generate a local voltage drop due to a parasitic body resistance. When the local voltage drop becomes large enough, such as when the voltage on drain region
120
exceeds the snapback voltage, the local voltage forward biases the p− body region
118
to n+ source region
122
junction. Forward biasing the junction, in turn, turns on a parasitic npn transistor. At this point, the cell enters a negative resistance region, known as the snapback region, and device failure typically occurs.
FIG. 4
shows a cross-sectional diagram that illustrates a single transistor cell
124
. As shown in
FIG. 4
, cell
124
includes a parasitic npn transistor
410
and a parasitic body resistance Rb. Body resistance Rb is formed by the n+ source region
122
pinching the p− body region
118
. Resistance Rb is high, having a typical value of 5,000 ohms/square for a 30V LDMOS process.
FIG. 5
shows a graph that illustrates a typical drain current characteristic of LDMOS transistor cell
124
. As shown in
FIG. 5
, a range of drain-to-source voltages Vds is plotted against a range of drain-to-source currents Ids. A number of gate-to-source voltage Vgs curves are plotted in FIG.
5
. On each curve is a circle that represents the snapback voltage.
In addition, a snapback line
510
is defined by joining together the snapback voltage circles on each gate-to-source curve. A safe operating area (SOA)
512
, in turn, is defined as the positive region to the left of snapback line
510
. The drain-to-source and gate-to-source voltage combinations that fall outside of safe operating area
512
typically lead to device failure.
As further shown in
FIG. 5
, as the gate-to-source voltage Vgs increases (by increasing the gate voltage when the source is connected to ground), LDMOS transistor
100
snaps back at lower and lower drain-to-source voltages (lower drain voltages when the source is connected to ground).
Although LDMOS transistor
100
operates satisfactorily, the restricted range of the safe operating area limits the usefulness of transistor
100
. Thus, there is a need for an LDMOS transistor with a larger safe operating area.
SUMMARY OF THE INVENTION
The present invention increases the safe operating area of a transistor by utilizing transistor cells with a crossed bar shaped body contact region and at least one smaller source region that adjoins the body contact region. The crossed bar shaped body contact region lowers the parasitic base resistance of the transistor which, in turn, increases the safe operating area.
A transistor in accordance with the present invention includes a first region of semiconductor material that has a first conductivity
Brisbin Douglas
Strachan Andy
Cao Phat X.
National Semiconductor Corporation
Pickering Mark C.
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