Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2011-06-21
2011-06-21
Louie, Wai-Sing (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S334000, C257S329000, C257S331000
Reexamination Certificate
active
07964913
ABSTRACT:
A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type.
REFERENCES:
patent: 5216275 (1993-06-01), Chen
patent: 5282018 (1994-01-01), Hiraki et al.
patent: 5637898 (1997-06-01), Baliga
patent: 5767548 (1998-06-01), Wondrak et al.
patent: 5864159 (1999-01-01), Takahashi
patent: 5973359 (1999-10-01), Kobayashi
patent: 5998833 (1999-12-01), Baliga
patent: 6069372 (2000-05-01), Uenishi
patent: 6078090 (2000-06-01), Williams et al.
patent: 6114727 (2000-09-01), Ogura et al.
patent: 6191447 (2001-02-01), Baliga
patent: 6251730 (2001-06-01), Luo
patent: 6388286 (2002-05-01), Baliga
patent: 6509233 (2003-01-01), Chang et al.
patent: 6525373 (2003-02-01), Kim
patent: 6541820 (2003-04-01), Bol
patent: 6649975 (2003-11-01), Baliga
patent: 6686244 (2004-02-01), Blanchard
patent: 6710403 (2004-03-01), Sapp
patent: 6803627 (2004-10-01), Pfirsch
patent: 7230310 (2007-06-01), Chen
patent: 2001/0041407 (2001-11-01), Brown
patent: 2003/0071616 (2003-04-01), Hauenstein
patent: 2003/0203576 (2003-10-01), Kitada et al.
patent: 2005/0032291 (2005-02-01), Baliga
patent: 2005/0056886 (2005-03-01), Tihanyi
patent: 2006/0060916 (2006-03-01), Girdhar et al.
patent: 2006/0118853 (2006-06-01), Takata et al.
patent: 2006/0214222 (2006-09-01), Challa et al.
patent: 2006/0267090 (2006-11-01), Sapp et al.
Grant et al.,Power MOSFETS Theory and Applications, John Wiley & Sons Ltd., 1989, p. 68-74.
Kazerounian et al., “CODMOS—A Depletion MOSFET Using Fixed Oxide Charge”, 41st Annual Device Research Conference,IEEE Electron Devices Society, Jun. 20-22, 1983.
Konig et al., “The Negatively Charged Insulator-Semiconductor Structure: Concepts, Technological Considerations and Applications,”.Solid State Electronics, 2000; 44(1): 111-116.
Pfiester et al., “Gain-enhanced LDD NMOS Device Using Cesium Implantation,”IEEE Transactions on Electron Devices, Jun. 1992; 39(6): 1469-1476.
International Search Report and Written Opinion of PCT Application No. PCT/US08/50505, dated Jul. 7, 2008, 17 pages total.
Watt et al. “A Low-Temperature NMOS Technology with Cesium-Implanted Load Devices” IEEE Trans. Electron Devices, 34, Jan. 1987, pp. 28-38.
J. T. Watt, B. J. Fishbein & J. D. Plummer; Low-Temperature NMOS Technology with Cesium-Implanted Load Devices; IEEE Trans.Electron Devices, vol. 34, # 1, Jan. '87; p. 28-38.
J.T.Watt,B.J.Fishbein & J.D.Plummer;Characterization of Surface Mobility in MOS Structures Containing Interfacial Cesium Ions;IEEE Trans.Electron Devices,V36,Jan. '89; p. 96-100.
J.R.Pfiester, J.R.Alvis & C.D.Gunderson; Gain-Enhanced LDD NMOS Device Using Cesium Implantation; IEEE Trans.Electron Devices, V39, #6, Jun. '92; p. 1469-1476.
Groover III Robert O.
Jahan Bilkis
Louie Wai-Sing
MaxPower Semiconductor Inc.
Storm LLP
LandOfFree
Power MOS transistor incorporating fixed charges that... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Power MOS transistor incorporating fixed charges that..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power MOS transistor incorporating fixed charges that... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2741455