Power MOS device

Details Power MOS device Power MOS device

2007-10-23

2007-10-23

Tran, Thien F (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S334000, C257S335000, C257S337000

Reexamination Certificate

active

11056346

ABSTRACT:
A semiconductor device comprises a drain, a body disposed over the drain, having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench having a trench wall and an anti-punch through implant that is disposed along the trench wall.A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a gate trench in the substrate, through the hard mask, depositing gate material in the gate trench, removing the hard mask to leave a gate structure, forming a source body contact trench having a trench wall and forming an anti-punch through implant.

REFERENCES:
patent: 5693569 (1997-12-01), Ueno
patent: 6710403 (2004-03-01), Sapp
patent: 6784505 (2004-08-01), Zeng
patent: 2004/0222457 (2004-11-01), Kim et al.
patent: 2005/0167742 (2005-08-01), Challa et al.

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