Power modeling methodology for a pipelined processor

Details Power modeling methodology for a pipelined processor Power modeling methodology for a pipelined processor

2005-05-17

2005-05-17

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C703S014000, C703S023000

Reexamination Certificate

active

06895561

ABSTRACT:
A method for modeling the power behavior of a pipelined processor has been developed. The method uses a power model integrated into a cycle accurate simulator. To create the power model, design blocks of the processor are divided into sub-blocks. Power modeling equations for each sub-block are developed by collaboration between the sub-block circuit designer and the simulator developer, using activity information relevant to the sub-block that is available in the simulator model. Each equation is calculated multiple times with different sets of power parameters to represent varying power conditions. Every simulation cycle, sub-block power is summed to generate full-chip power for multiple power conditions.

REFERENCES:
patent: 5625803 (1997-04-01), McNelly et al.
patent: 5692160 (1997-11-01), Sarin
patent: 5838947 (1998-11-01), Sarin
Katkoori et al., Simulation based Architectural Power Estimation for PLA-based Controllers, Internation Symposium on Low Power Electronics and Design, pp. 121-124, Aug. 1996.

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