Power mode control method and circuitry

Details Power mode control method and circuitry Power mode control method and circuitry

2011-01-25

2011-01-25

Stiglic, Ryan M (Department: 2111)

Electrical computers and digital processing systems: support

Computer power control

By external command

C713S330000, C713S340000

Reexamination Certificate

active

07877619

ABSTRACT:
In some embodiments, a power up (or power mode) interface is provided whereby a chip's power up signals are encoded into multiple states to provide more functions than the number of signals used to define the states.

REFERENCES:
patent: 5251320 (1993-10-01), Kuzawinski et al.
patent: 6498523 (2002-12-01), Gebara
patent: 7051218 (2006-05-01), Gulick et al.
patent: 7290127 (2007-10-01), Schmisseur et al.
patent: 7519839 (2009-04-01), Diefenbaugh et al.
patent: 2007/0079162 (2007-04-01), Mundada et al.
patent: 2008/0091959 (2008-04-01), Yu et al.
patent: 2008/0191331 (2008-08-01), Lee et al.
patent: 2010/0188133 (2010-07-01), Burdett

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