Power metal oxide semiconductor field effect transistor layout

Details Power metal oxide semiconductor field effect transistor layout Power metal oxide semiconductor field effect transistor layout

2005-05-03

2005-05-03

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S342000, C257S288000, C257S327000, C257S335000

Reexamination Certificate

active

06888197

ABSTRACT:
A power MOSFET layout according to one embodiment of the invention comprises a substrate and a plurality of cells. Each of the cells includes a base portion, a plurality of protruding portions extending from the base portion, and a plurality of photo-resist regions. Each of the cells is geometrically configured with the base portion and the plurality of protruding portions defining a closed cell boundary enclosing each of said cells. The cells are formed over the substrate, and the closed cell boundaries of the cells are arranged regularly with each other with no overlapping among the cells. The base portions are disposed in a matrix arrangement having rows and columns. The base portions are oriented from end to end in a direction of the columns and the protruding portions extend from the base portions along a direction of the rows. The photo-resist regions cover the base portions on the same column. None of the protruding portions are disposed between the base portions on the same column. The cells are doped with N type dopants by using the photo-resist regions as masks.

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