Electrical computers and digital processing systems: support – Computer power control
Reexamination Certificate
2001-12-05
2004-12-28
Lee, Thomas (Department: 2115)
Electrical computers and digital processing systems: support
Computer power control
C327S603000
Reexamination Certificate
active
06836848
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention concerns an integrated circuit. More specifically, an integrated circuit for assisting with power-management functions of a central processing unit is disclosed.
2. Description of the Prior Art
The motherboards of computer systems have a number of components that are used to interface the central processing unit (CPU) with other devices. Each of these components must be laid out and soldered onto the motherboard. Some of the most recent CPUs now available on the market, such as the K
7
CPU from Advanced Micro Devices (AMD), have new power management functions that include adjusting the internal operating frequency of the CPU and changing the core voltage of the CPU. When the CPU is running at a lower internal frequency, a lower core voltage may be used. Adjustments to the internal operating mode of the CPU may thereby be made that exchange processing power for reduced consumption of electrical power. This is extremely beneficial in the realm of portable computing, where users wish to extend battery life for as long as possible. An advanced CPU like the K
7
is, for most applications, more than sufficiently powerful to handle tasks even at a reduced rate of processing ability.
Unfortunately, to facilitate these power management functions of the CPU, more components are required on the motherboard. Specifically, one set of components is required to interface the voltage regulating abilities of the CPU with the power regulator of the motherboard, and another set of components is required to interface the frequency-adjusting abilities of the processor with the north bridge chipset. As an increase in the total number of components on the motherboard tends to make for a more complicated layout, and requires more soldering during manufacturing of the motherboard, a higher price is incurred by these extra components. Also, these additional components require extra space on the motherboard, space which may already be at a premium.
SUMMARY OF INVENTION
It is therefore a primary objective of this invention to provide an integrated circuit that manages both the voltage regulating and frequency regulating signals coming from a CPU to interface the CPU with other components, notably the north bridge chipset and the power regulator.
The present invention, briefly summarized, discloses an integrated circuit for supporting a processing system. The processing system has a central processing unit (CPU), a north bridge circuit, a south bridge circuit and a power regulator for providing a core voltage to the CPU. The core voltage is provided according to a VID value provided by a plurality of VID_PWM input lines for the power regulator. The integrated circuit includes a CPU_SELECT input line for indicating a type of the CPU as being either desktop or mobile, VID_SOFT input lines for indicating a programmable core voltage requested by the CPU, VID_CPU input lines for indicating a default core voltage of the CPU, a CPUSTOP# input line for indicating a sleep state of the CPU, FID_CPU input lines for indicating a CPU operating frequency, a plurality of power signal input lines, a power detection circuit for determining the suitability of electrical power provided by the power regulator according to the power signal input lines and generating an associated PWRGOOD# signal line, a default sleep VID value corresponding to a default sleep voltage for the CPU, a programmable VID override table, a programmable FID override table, a serial data input line for programming the VID override table and the FID override table, VID_PWM output lines for passing the VID value to the VID_PWM input lines of the power regulator, a VID logic circuit for generating the VID value, FID_CHIP output lines for providing an FID value to the north bridge circuit and the south bridge circuit, a plurality of FID_OVERRIDE output lines for providing the FID value to the CPU, and an FID logic circuit for generating the FID value. The VID value is set equal to one of the following by the VID logic circuit: a value in the programmable VID override table if the programmable VID override table has been programmed by the serial data input line, the value of the VID_SOFT input lines if the CPU_SELECT input line indicates a mobile-type CPU and the PWRGOOD# signal line indicates suitable power conditions, the value of the VID_CPU input lines if the CPU_SELECT input line indicates a mobile-type CPU and the PWRGOOD# signal line indicates unsuitable power conditions, the value of the VID_CPU input lines if the CPU_SELECT input line indicates a desktop-type CPU and the PWRGOOD# signal line indicates suitable power conditions, or the value of the default sleep VID lines if the CPU_SELECT input line indicates a desktop-type CPU and the PWRGOOD# signal line indicates unsuitable power conditions or the CPUSTOP# input line indicates that the CPU is in the sleep state. The FID value is equal to one of the following by the FID logic circuit: a value in the programmable FID override table if the programmable FID override table has been programmed by the serial data input line, or the value of the FID_CPU input lines.
It is an advantage of the present invention that the integrated circuit provides a single package that handles interfacing the power saving functionality of the CPU with other devices. By providing a single package, costs are lowered, space is saved on the motherboard and the motherboard layout is simplified. Additionally, the present invention integrated circuit offers flexibility in that it may be applied to both mobile and desktop type CPUs. Utilizing a serial interface to program the override FID and VID values in the programmable tables reduces the pin count on the circuit package, and hence layout dimensions.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.
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patent: 6035407 (2000-03-01), Gebara et al.
patent: 6601179 (2003-07-01), Jackson et al.
patent: 6691235 (2004-02-01), Garcia et al.
patent: 6697952 (2004-02-01), King
patent: 6732266 (2004-05-01), Anderson et al.
Philips Semiconductors, “PCA9559—System Management ICs”, 2000.*
Philips Semiconductors, “PCA9559 5-Bit Multiplexed/1-Bit Latched 6-Bit 12C EEPROM”, Data Sheet, Jan. 2000.*
California Micro Devices, “CMBUS100—AMD Athlon VID/FID Interface”, Data Sheet, Mar. 2002.*
Attansic Technology, “ATXP1—Jumper Free Over Clock Controller”, Data Sheet, Revision 1.01, Sep. 2001.
Chang Nai-Shung
Yu Chia-Hsing
Hsu Winston
Lee Thomas
VIA Technologies Inc.
Wang Albert
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