Power management independent of CPU hardware support

Electrical computers and digital processing systems: support – Computer power control – Power conservation

Reexamination Certificate

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Details

C713S320000

Reexamination Certificate

active

07853817

ABSTRACT:
A system including power savings modes, the system including a processor that supports bus semantics in its hardware for a power state of a first level, wherein the first level is lowest power level the processor is able to enter, a system core logic module coupled to the processor, and a memory, coupled to the system core logic module, storing instructions, which when executed by the system, causes the system core logic to be notified of an impending processor idle state that is compatible with the latency required for system core logic power savings modes and wherein, in response to being notified of an impending processor idle state, the system core logic implements thread, core, or package level power saving idle modes lower than supported by the first level based on a latency hierarchy and independent of normal power saving bus semantics.

REFERENCES:
patent: 6823516 (2004-11-01), Cooper
patent: 2005/0166073 (2005-07-01), Lee
patent: 2008/0052543 (2008-02-01), Sokorac
patent: 2010/0058078 (2010-03-01), Branover et al.
“Advanced Configuration and Power Interface Specification”, Hewlett-Packard/Intel/Microsoft/Phoenix/Toshiba. Dec. 30, 2005, 624 pages, 373 pages.

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