Electrical computers and digital processing systems: support – Computer power control – Power conservation
Patent
1998-05-28
2000-10-03
Auve, Glenn A.
Electrical computers and digital processing systems: support
Computer power control
Power conservation
713324, G06F 132
Patent
active
061287458
ABSTRACT:
A method for managing power in an electronic system having a plurality of input/output devices, each of the input/output devices having a full power-on state and at least one power reduction state and each being controlled by an associated device driver, the method comprising the steps of: initializing a power management logic separate from the device drivers to receive at least one time-out value for each of the device drivers to be subject to power management; assigning a different timer in the power management logic to a different one of the device drivers to be subject to power management, the timers being disposed external of the device drivers; initializing each of a plurality of the assigned timers to individual predetermined value set in accordance with the at least one time out value of the assigned device driver for that timer; changing the individual predetermined value held in each of the timers at a predetermined interval; monitoring a plurality of the timers and determining when the predetermined value in one of the timers indicates that the time-out value for the assigned device driver has elapsed, and sending a power reduction instruction to the assigned device driver; and resetting a given one of the timers to its individual predetermined value at any time when the device driver associated with the timer indicates a usage event of its associated device driver, and powering the associated device to a higher power level if it is not at full power-on.
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Tatsu, Nakazato, JP doc. No. 10124201, May 15, 1998, Patent Abstracts of Japan.
Anderson Eric Christopher
Farhi Henri Hayim
Auve Glenn A.
Phoenix Technologies Ltd.
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