Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
2009-01-20
2011-12-13
Stiglic, Ryan (Department: 2111)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S330000
Reexamination Certificate
active
08078897
ABSTRACT:
This invention is a power management scheme for a shared memory multiprocessor system which splits the control logic between the master-specific logic and memory bank logic. Power-down is initiated from a central power-down controller. This central power-down controller informs the master and target specific logic. Further memory accesses are blocked. All pending activities complete. The central controller then proceeds to power down the memory and informs the master and target specific logic upon completion. No requests for wakeup are initiated by master-specific logic from the time a power-down request is received until the completion of power-down.
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patent: 2008/0313482 (2008-12-01), Karlapalem et al.
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Anand Alok
Sajayan Sajish
Surendran Sudhakar
Brady W. James
Marshall, Jr. Robert D.
Stiglic Ryan
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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