Power management in digital receivers that adjusts at least...

Details Power management in digital receivers that adjusts at least... Power management in digital receivers that adjusts at least...

2006-05-02

2009-06-30

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C375S316000, C455S574000

Reexamination Certificate

active

07555661

ABSTRACT:
Methods and systems consistent with the present invention provide a method for dynamically controlling power consumption in a digital demodulator circuit by varying clock rates and bit widths of demodulator components including an analog to digital converter, decimation filter, OFDM operating engine, FEC decoder, and MPE-FEC processor, according to parameters and conditions of the received signal including modulation mode, signal to noise ratio, effective bit transmission rate, bit error rate, packet error rate, adjacent channel interference, and co-channel interference.

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PCT International Search Report, Mar. 20, 2008.

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