Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies
Reexamination Certificate
2011-06-21
2011-06-21
Lee, Thomas (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Multiple or variable intervals or frequencies
C713S100000
Reexamination Certificate
active
07966511
ABSTRACT:
Systems and methods of managing power provide for issuing a first operating requirement from a first processor core and issuing a second operating requirement from a second processor core. In one embodiment, the operating requirements can reflect either a power policy or a performance policy, depending upon the factor that is currently most important to software. Hardware coordination logic is used to coordinate a shared resource setting with the operating requirements. The hardware coordination logic is also able to coordinate the shared resource setting with independent resource settings of the first and second processor cores based on the operating requirements.
REFERENCES:
patent: 5307003 (1994-04-01), Fairbanks et al.
patent: 5502838 (1996-03-01), Kikinis
patent: 5526487 (1996-06-01), Schiffleger
patent: 5592671 (1997-01-01), Hirayama
patent: 5627412 (1997-05-01), Beard
patent: 5745375 (1998-04-01), Reinhardt et al.
patent: 5787294 (1998-07-01), Evoy
patent: 5812860 (1998-09-01), Horden et al.
patent: 5862368 (1999-01-01), Miller et al.
patent: 5870616 (1999-02-01), Loper et al.
patent: 5918061 (1999-06-01), Nikjou
patent: 5953685 (1999-09-01), Bogin
patent: 6047248 (2000-04-01), Georgiou
patent: 6115763 (2000-09-01), Douskey et al.
patent: 6363490 (2002-03-01), Senyk
patent: 6415388 (2002-07-01), Browning et al.
patent: 6438658 (2002-08-01), Baliga et al.
patent: 6550020 (2003-04-01), Floyd et al.
patent: 6691216 (2004-02-01), Kelly et al.
patent: 6711447 (2004-03-01), Saeed
patent: 6711691 (2004-03-01), Howard et al.
patent: 6714891 (2004-03-01), Dendinger
patent: 6729551 (2004-09-01), Dia
patent: 6804790 (2004-10-01), Rhee et al.
patent: 6885233 (2005-04-01), Huard et al.
patent: 6983386 (2006-01-01), Barr et al.
patent: 7043405 (2006-05-01), Orenstien et al.
patent: 7043649 (2006-05-01), Terrell, II
patent: 7076672 (2006-07-01), Naveh
patent: 7127560 (2006-10-01), Cohen et al.
patent: 7134031 (2006-11-01), Flautner
patent: 7136984 (2006-11-01), Maiyuran et al.
patent: 7437513 (2008-10-01), Saida et al.
patent: 7502887 (2009-03-01), Tanaka
patent: 7546418 (2009-06-01), Verdun
patent: 2002/0083356 (2002-06-01), Dai
patent: 2002/0095610 (2002-07-01), Nunomura
patent: 2003/0101362 (2003-05-01), Dia
patent: 2004/0098631 (2004-05-01), Terrell, II
patent: 2004/0098635 (2004-05-01), Terrell et al.
patent: 2004/0117678 (2004-06-01), Soltis
patent: 2006/0047986 (2006-03-01), Kurts et al.
patent: 2006/0053326 (2006-03-01), Naveh
patent: 2006/0143485 (2006-06-01), Naveh et al.
patent: 2007/0043965 (2007-02-01), Mandelblat
patent: 2007/0137036 (2007-07-01), Jahagirdar
patent: 2007/0156992 (2007-07-01), Jahagirdar
patent: 2007/0157036 (2007-07-01), Jahagirdar
patent: 1993669 (2007-07-01), None
patent: 0 978 781 (1999-07-01), None
patent: 0978781 (1999-07-01), None
patent: 0978781 (2000-02-01), None
patent: 1 286 248 (2003-02-01), None
patent: 1 286 248 (2003-02-01), None
patent: 142 628 (2004-06-01), None
patent: 1 286 248 (2006-02-01), None
patent: 1009 1603 (1998-04-01), None
patent: 2000-066776 (2000-03-01), None
patent: 200625069 (2006-07-01), None
patent: WO0101228 (2001-04-01), None
patent: WO 01/35200 (2001-05-01), None
patent: WO 01-35200 (2001-05-01), None
patent: WO 02/17052 (2002-02-01), None
patent: WO 02-17052 (2002-02-01), None
patent: WO 2005/048112 (2005-05-01), None
U.S. Appl. No. 10/272,149; Title: Method and Apparatus for Performance Effective Power Throttling; Inventor: Alon Naveh; Filing Date: Oct. 14, 2002.
U.S. Appl. No. 11/208,935 Title: Dynamic Memory Sizing for Power Reduction; Inventor: Julius Mandelblat; Filing Date: Aug. 22, 2005.
U.S. Appl. No. 10/934,034; Title: Coordination of Sleep State Transitions in Multi-Core; Inventor: Alon Naveh; Filing Date: Sep. 3, 2004.
U.S. Appl. No. 11/323,259; Title: Method and System for Optimizing Latency of Dynamic Memory Sizing; Inventor: Sanjeev Jahagirdar; Filing date: Dec. 30, 2005.
U.S. Appl. No. 11/323,254; Title: Method and Apparatus for a Zero Voltage Processor Sleep; Inventor: Sanjeev Jahagirdar; Filing Date: Dec. 30, 2005.
Invitation to Pay Additional Fees and Annex (partial International Search) from PCT/US2005/028699, mailed Mar. 2, 2006, 10 pages.
International Search Report for corresponding matter P15271PCT dated May 28, 2004.
Notice of Allowance for related matter P15271, U.S. Appl. No. 10/272,149 dated Jan. 5, 2006.
International Search Report and Written Opinion for related matter P20418PCT mailed May 8, 2006.
Invitation to Pay Additional Fees and Annex (partial International Search) for related matter P20418PCT mailed Mar. 2, 2006.
“Advanced Configuration and Power Interface Specification”, Compaq Computer Corporation, Intel Corporation, Microsoft Corporation, Phoenix Technologies Ltd., Toshiba Corporation, Revision 2.0b, Chapter 8, pp. 219-232, Oct. 11, 2002.
International Search Report for related matter P22435PCT, mailed Jun. 6, 2007.
International Preliminary Report on Patentability for related matter P22435PCT.
Written Opinion of the International Searching Authority for related matter P22435PCT.
USPTO Notice of Allowance Mailed Jul. 1, 2008 for U.S. Appl. No. 10/934,034, Whole Document.
Taiwanese Office Action Mailed Aug. 13, 2009 for Taiwanese Patent Application No. 94124132, Whole Document with English Translation.
Chinese Office Action Mailed Jan. 9, 2009 for Chinese Patent Application No. 200580025704.3, Whole Document with English Translation.
Itoh, Tomoya , et al., “42P19740JP, Office Action mailed Jan. 5, 2010, for JP Appl. No. 2007-522581, 3 pages”.
Office Action dated Apr. 7, 2010 for 112005001779.6 6pgs.
Second Office Action mailed Mar. 25, 2010 for CN200580025704.3 19 pgs.
Office Action dated Jan. 5, 2010 for 2007-522581 6pgs.
International Search Report and Written Opinion dated Feb. 1, 2006, for PCTUS0525088 12pgs.
International Preliminary Report on Patentability dated Feb. 8, 2007 for PCTUS0525088 7pgs.
Office Action dated Aug. 25, 2010 for 112005001779.6 4 pages.
Office Action dated Sep. 28, 2010 for 2007-522581 6 pages.
Naveh Alon
Rotem Efraim
Weissmann Eliezer
Blakely , Sokoloff, Taylor & Zafman LLP
Chang Eric
Intel Corporation
Lee Thomas
LandOfFree
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