Power management block for use in a non-volatile memory system

Details Power management block for use in a non-volatile memory system Power management block for use in a non-volatile memory system

2006-12-27

2010-10-05

Cao, Chun (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

C713S001000, C713S002000, C713S100000, C711S102000, C711S103000, C711S156000

Reexamination Certificate

active

07809962

ABSTRACT:
Methods and apparatus for enabling a power up process of a non-volatile memory to occur efficiently are disclosed. According to one aspect of the present invention, a method for utilizing a memory system that has a non-volatile memory with at least one reserved memory area includes providing power to the memory system, initializing the non-volatile memory, and writing a first signature into the reserved memory area. The first signature is arranged to indicate that the memory system was successfully initialized. In one embodiment, the method also includes executing a power down process on the memory system, and writing a second signature into the reserved memory area which indicates that the power down process has been executed.

REFERENCES:
patent: 5222109 (1993-06-01), Pricer
patent: 5297148 (1994-03-01), Harari et al.
patent: 5388083 (1995-02-01), Assar et al.
patent: 5438573 (1995-08-01), Mangan et al.
patent: 5557777 (1996-09-01), Culbert
patent: 5568439 (1996-10-01), Harari
patent: 5598370 (1997-01-01), Niijima et al.
patent: 5748940 (1998-05-01), Angelo et al.
patent: 5835935 (1998-11-01), Estakhri et al.
patent: 5845313 (1998-12-01), Estakhri et al.
patent: 5860082 (1999-01-01), Smith et al.
patent: 5907856 (1999-05-01), Estakhri et al.
patent: 5924113 (1999-07-01), Estakhri et al.
patent: 6016275 (2000-01-01), Han
patent: 6081447 (2000-06-01), Lofgren et al.
patent: 6115785 (2000-09-01), Estakhri et al.
patent: 6125435 (2000-09-01), Estakhri et al.
patent: 6154808 (2000-11-01), Nagase et al.
patent: 6216226 (2001-04-01), Agha et al.
patent: 6230233 (2001-05-01), Lofgren et al.
patent: 6260156 (2001-07-01), Garvin et al.
patent: 6426893 (2002-07-01), Conley et al.
patent: 6510488 (2003-01-01), Lasser
patent: 6820196 (2004-11-01), Kessler
patent: 6915440 (2005-07-01), Berglund et al.
patent: 7191296 (2007-03-01), Yoshii et al.
patent: 2002/0083368 (2002-06-01), Abe et al.
patent: 62-283496 (1987-12-01), None
patent: 62-283497 (1987-12-01), None
patent: 08-030520 (1998-02-01), None
Kim et al., “A Space-Efficient Flash Translation Layer for Compactflash Systems,” Trans. Cons Elec., vol. 48, No. 2 (IEEE, May 2002).
English translation of Office Action dated Apr. 3, 2009 in related Japanese Patent App. No. 2003-368140.

Affiliated with

Also associated with

Rating

Power management block for use in a non-volatile memory system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Power management block for use in a non-volatile memory system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power management block for use in a non-volatile memory system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4225721