Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2006-02-14
2006-02-14
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S024000, C714S027000, C713S340000
Reexamination Certificate
active
07000146
ABSTRACT:
A memory system provides one or more control signals for configuring and controlling a memory sub-system during a power failure or system reset. A power delay circuit and a power fail controller cooperate to quickly place the memory system in a retention state in the event a power failure event is detected. The power delay circuit detects either a reset signal or power failure to initiate the memory retention state. The power delay circuit and power fail controller ensure the memory system is initialized prior to entering the retention state.
REFERENCES:
patent: 4777626 (1988-10-01), Matsushita et al.
patent: 5182687 (1993-01-01), Campbell et al.
patent: 5742800 (1998-04-01), Forehand
patent: 6556487 (2003-04-01), Ratnakumar et al.
Bissessur Sailesh
Luckett Richard P.
Mackey Richard P.
Warren James D.
Beausoliel Robert
Pedigo Philip A.
Puente Emerson
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