Power line noise prevention circuit for semiconductor memory dev

Details Power line noise prevention circuit for semiconductor memory dev Power line noise prevention circuit for semiconductor memory dev

1997-06-04

1999-07-20

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Noise suppression

365226, G11C 702

Patent

active

059264276

ABSTRACT:
A power line noise prevention circuit for a semiconductor memory device which can suppress noises on supply and ground voltage lines with no conventional degradation in operation speed when internal circuits consuming a large current amount are sequentially operated. When a plurality of data output buffers output high data at the same time, the power line noise prevention circuit applies a high voltage to the supply voltage line for the operation time to prevent a supply voltage from being reduced in level. To the contrary, when a plurality of data output buffers output low data at the same time, the power line noise prevention circuit applies a substrate voltage to the ground voltage line for the operation time to prevent a ground voltage from being increased in level.

REFERENCES:
patent: 4883978 (1989-11-01), Ohshima et al.
patent: 4972100 (1990-11-01), Lim et al.
patent: 5341338 (1994-08-01), Hashiguchi
patent: 5619465 (1997-04-01), Nomura

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