Power level sensing for mixed voltage chip design

Details Power level sensing for mixed voltage chip design Power level sensing for mixed voltage chip design

1995-12-11

1997-10-07

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327 57, 327 77, H03L 700

Patent

active

056752725

ABSTRACT:
A power supply voltage level sensing circuit and its application to circuits that interface with circuits that have performance characteristics that conform to universally accepted standards such as TTL, is described. An input terminal of a threshold shifting means is connected to the power supply to be detected to shift the voltage level of the power supply to a level acceptable by a Schmitt trigger. The threshold voltage level of the Schmitt is set so as to detect the range of the voltages that may be present at the power supply. The output of the Schmitt trigger is the data input to a first flip-flop. A system reset terminal provides a power-on-reset signal to a reset terminal of the first flip-flop and to the clock input of the first flip-flop through a buffer circuit. The power-on-reset signal maintains the output of the first flip-flop at a first level for a period of time after the activation of the power supply. As the power supply achieves is proper operating voltage, the output of the Schmitt trigger will remain at a first level if the voltage of the power supply is lower than the threshold of the Schmitt trigger and assume a second level if the voltage of the power supply is greater than the threshold of the Schmitt trigger. As the power-on-reset changes from a first level to a second level, the data input of the first flip-flop transfers the appropriate level to indicate the power supply voltage level to external circuitry. A second flip-flop will deactivate the Schmitt trigger after the power supply has assumed its correct level and the first flip-flop has transferred the correct signal to the external circuitry.

REFERENCES:
patent: 5343086 (1994-08-01), Fung et al.
patent: 5420798 (1995-05-01), Lin et al.
patent: 5442586 (1995-08-01), Javaniford et al.

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