Power integrated circuit with latch-up prevention

Details Power integrated circuit with latch-up prevention Power integrated circuit with latch-up prevention

1992-04-14

1993-09-07

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257549, 257547, 257500, 257373, H01L 2714

Patent

active

052432149

ABSTRACT:
A power integrated circuit includes a substrate with an overlying epitaxial surface layer of opposite conductivity type. A semiconductor power device, such as a high-power diode or lateral MOS transistor, is located in the epitaxial layer and forms a p-n junction diode with the substrate. The power integrated circuit also includes a separate semiconductor well region in the epitaxial layer, in which one or more low-power semiconductor circuit elements are formed. In order to minimize the problem of latch up in the low-power circuit elements due to the injection of minority carriers from the substrate, the power integrated circuit is provided with a collector region and an isolation region between the power device and the well region having the low-power circuit elements.

REFERENCES:
patent: 3649887 (1972-03-01), Keller et al.
patent: 3931634 (1976-01-01), Knight
patent: 4170501 (1979-10-01), Khajezadeh
patent: 4466011 (1984-08-01), Van Zanten
patent: 4647956 (1987-03-01), Shrivastava et al.
patent: 4862233 (1987-06-01), Matsushita et al.
patent: 4890149 (1989-12-01), Bertotti et al.
patent: 4952998 (1989-04-01), Ludikhuize
Troutman, "Epitaxial Layer Enhancement of N-Well Guard Rings for CMOS Circuit," IEEE Electron Device Letters, vol. EDL-4, No. 12, Dec. 1983, pp. 438-440.

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