Power insulated-gate transistor having three terminals and a man

Details Power insulated-gate transistor having three terminals and a man Power insulated-gate transistor having three terminals and a man

1995-06-29

1998-03-17

Dang, Trung

Fishing, trapping, and vermin destroying

437 26, 437 27, 437 31, 437 41RBP, H01L 21265

Patent

active

057285934

ABSTRACT:
The present invention relates to a method of manufacturing an insulated-gate transistor including a very thin P.sup.- layer as a channel under a gate terminal. The device and method differs from conventional devices and techniques in that the P.sup.- regions are formed by double diffusion. Secondly, the present invention includes channel regions by forming the N.sup.+ regions in the middle of the shallow P.sup.- layer causing the resistance of the JFET regions to be reduced. High-speed operation of the device can be obtained by reducing the input and reverse capacitances which thereby reduces the time delay when power is supplied. The forward voltage drop is reduced by reducing the resistance of the first conductive semiconductor region which is determined by the distance between the second conductive type semiconductor region in its forward turn-on state.

REFERENCES:
patent: 4810665 (1989-03-01), Chang et al.
patent: 5023191 (1991-06-01), Sakurai
patent: 5084401 (1992-01-01), Hagino
patent: 5164327 (1992-11-01), Maruyama

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