Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2001-12-19
2004-10-05
Kang, Donghee (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S779000, C257S780000, C257S784000, C257S787000
Reexamination Certificate
active
06800944
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the packaging of integrated circuits (IC's), and more particularly to circuit boards or substrates for mounting and packaging IC's.
BACKGROUND
Semiconductors are used for integrated circuits for electronic applications, including radios, televisions, cell phones, and personal computing devices, as examples. With the trend towards miniaturization of electronic devices, there is a trend towards making IC's and the packages thereof smaller.
One result of the IC miniaturization trend is the development of ball grid array (BGA) and chip scale packages (CSP's). These packages utilize surface-mount technologies in which the IC is coupled to a substrate by surface contacts rather than through-hole connections, as used in prior art dual in-line (DIP) packages, for example. A ball grid array package comprises a series of terminals on the underside of an integrated circuit that are substantially spherical in shape. These terminals may be arranged in multiple rows around the periphery of the underside of the integrated circuit. Because multiple rows can be used, a higher number of terminals can exist in a ball grid array package in comparison to some other technologies. Typically, a ball grid array is connected to a printed circuit board by soldering the balls to contacts on the printed circuit board.
Another type of surface mount IC package is a chip scale package. A working definition of the term chip scale package as used herein typically refers to a package that is about 1.2 times the size (length and/or width) of the IC chip (die) or less, or 1.2 times the area, e.g., for chip having an area of 100 square mil
2
, the package is around 120 mil
2
or less, e.g., the package is slightly larger than the chip. A chip scale package permits an integrated circuit to be attached to a printed-circuit (PC) board face up or face-down, with the integrated circuit's pads connecting to the PC board's pads through individual balls of solder.
SUMMARY OF THE INVENTION
Preferred embodiments of the present invention achieve technical advantages as a substrate and package for an integrated circuit chip having a conductive ring around the perimeter of the contact terminals, which may be used as a ground or power ring.
In one embodiment, disclosed is a substrate for an unpackaged integrated circuit chip having surface mount contacts disposed thereon in a pattern. The substrate includes an insulating material and a conductive material disposed over the insulating material. The conductive material comprises a plurality of contacts arranged in a pattern corresponding to the integrated circuit contact pattern. The conductive material also comprises a conductive ring disposed around the periphery of the contact pattern. The substrate contacts are coupleable to the integrated circuit chip surface mount contacts.
In another embodiment, disclosed is a package for an integrated circuit chip having surface mount contacts disposed thereon in a pattern. The package includes a substrate having an insulating material and a conductive material disposed over the insulating material. The conductive material comprises a plurality of contacts arranged in a pattern corresponding to the integrated circuit contact pattern. The conductive material also comprises a conductive ring disposed around the periphery of the contact pattern. The substrate contacts are coupleable to the integrated circuit chip surface mount contacts.
In another embodiment, disclosed is a method of manufacturing a substrate for an unpackaged integrated circuit chip having surface mount contacts disposed thereon in a pattern. The method comprises providing an insulating material, disposing a conductive material over the insulating material, and patterning the conductive material to form a plurality of contacts arranged in a pattern corresponding to the integrated circuit contact pattern. The method includes forming a ring in the conductive material around the periphery of the conductive material contact pattern. The substrate contacts are coupleable to the integrated circuit chip surface mount contacts.
Advantages of embodiments of the present invention include providing a conductive ring around contacts of surface mount integrated circuit chip, which may be used for shielding or for providing power. Individual contacts or terminals may be completely surrounded by a ground signal, which is particularly advantageous for coaxial connections, high-speed applications, or sensitive signals. Groups of contacts or terminals may also be shielded, which is advantageous in certain design scenarios. A substrate having a conductive ring in accordance with embodiments of the present invention may be covered with an insulative material, and the insulative material may be coated with a conductive or dissipative material that makes electrical contact to the conductive ring to provide a completely electromagnetic interference (EMI)/radio frequency interference (RFI) shielded package. Advantageously, the conductive ring may be formed when the contact terminals and/or traces of the substrate are patterned.
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Brady III W. James
Kang Donghee
Vu Quang
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