Power-ground plane for a C4 flip-chip substrate

Details Power-ground plane for a C4 flip-chip substrate Power-ground plane for a C4 flip-chip substrate

1997-10-07

1999-03-23

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

257700, 257691, H01L 2304

Patent

active

058864067

ABSTRACT:
A package for an integrated circuit that contains a plurality of small circular dielectric spaces which separate vias from a conductive plane of the package. The package has a first internal conductive plane, a second internal conductive plane and a plurality of bond pads located on a top surface of a substrate. The substrate has a plurality of vias that extend through the first conductive plane to couple the second conductive plane to the bond pads. The package has a plurality of concentric dielectric clearance spaces that separate the vias from the first conductive plane. The small concentric spaces optimize the area of the conductive plane to minimize the resistance and maximize the capacitance of the package.

REFERENCES:
patent: 4667219 (1987-05-01), Lee et al.
patent: 5099388 (1992-03-01), Ogawa et al.
patent: 5450290 (1995-09-01), Boyko et al.
patent: 5538433 (1996-07-01), Arisaka
patent: 5708296 (1998-01-01), Bhansali

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