Power grid layout techniques on integrated circuits

Details Power grid layout techniques on integrated circuits Power grid layout techniques on integrated circuits

2006-02-14

2006-02-14

Clark, Jasmine J. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

C257S691000, C257S207000, C257S208000

Reexamination Certificate

active

06998719

ABSTRACT:
Techniques are provided for reducing power supply voltage drop introduced by routing conductive traces on an integrated circuit. Techniques for reducing variations in the power supply voltages received in different regions of an integrated circuit are also provided. Power supply voltages are routed within an integrated circuit across conductive traces. The conductive traces are coupled to bond pads that receive power supply voltages from an external source. Alternate ones of the traces receive a high power supply voltage VDDand a low power supply voltage VSS. The conductive traces reduce the voltage drop in the power supply voltages by providing shorter paths to route the power supply voltages to circuit elements on the integrated circuit.

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