Power gating structure having data retention and...

Details Power gating structure having data retention and... Power gating structure having data retention and...

2007-03-13

2007-03-13

Le, Don (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

C326S082000

Reexamination Certificate

active

11129749

ABSTRACT:
The present invention provides a power gating structure having data retention and intermediate modes and able to operate under multiple modes. A conventional power gating structure has only turn-on and turn-off functions, and is used to suppress a leakage current problem which has become more and more serious in advance manufacture processes, under a turn-off mode. However, in a memory circuit, such as latch, register and SRAM, when the power gate is turned off, a new power gating structure is required for data retention. The power gating structure of the present invention can be set into one of 4 different operational modes: a data retention mode for maintaining the static noise margin of the memory, an intermediate mode for reducing the interference on ground and power levels, an active mode used when the circuit operates in normal condition, and a standby mode used when the circuit does not operate.

REFERENCES:
patent: 6552601 (2003-04-01), Burr
patent: 2003/0197544 (2003-10-01), Burr
patent: 2006/0145726 (2006-07-01), Hidaka

Affiliated with

Also associated with

Rating

Power gating structure having data retention and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Power gating structure having data retention and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power gating structure having data retention and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3761038