Power gating schemes in SOI circuits in hybrid SOI-epitaxial...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S350000, C257S369000, C257SE27064

Reexamination Certificate

active

07342287

ABSTRACT:
Disclosed are a multi-threshold CMOS circuit and a method of designing such a circuit. The preferred embodiment combines an MTCMOS scheme and a hybrid SOI-epitaxial CMOS structure. Generally, the logic transistors (both nFET and pFET) are placed in SOI, preferably in a high-performance, high density UTSOI; while the headers or footers are made of bulk epitaxial CMOS devices, with or without an adaptive well-biasing scheme. The logic transistors are based on (100) SOI devices or super HOT, the header devices are in bulk (100) or (110) pFETs with or without an adaptive well biasing scheme, and the footer devices are in bulk (100) NFET with or without an adaptive well biasing scheme.

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