Power failure mode for a memory controller

Details Power failure mode for a memory controller Power failure mode for a memory controller

1998-06-19

2000-07-11

Lane, Jack A.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

365222, 365226, 365228, G06F 1216, G11C 11406

Patent

active

060887621

ABSTRACT:
A power failure mode for a memory controller, such as a memory controller used in an input/output processor, which, when the memory controller has system power, refreshes a memory unit, such as an SDRAM memory unit, as required to maintain the memory image. In one embodiment, when a power failure occurs, the memory controller issues a self-refresh command to the memory, which has battery-backup power. A PCI reset signal may be used to determine when a power failure has occurred. The self-refresh command places the memory in a self-refresh mode, and a programmable logic device may be used to ensure that a clock enable signal input to the memory maintains the self-refresh mode. When system power returns, the memory controller resumes refreshing the memory.

REFERENCES:
patent: 5229970 (1993-07-01), Lee et al.
patent: 5323354 (1994-06-01), Matsumoto et al.
patent: 5630090 (1997-05-01), Keehn et al.
patent: 5640357 (1997-06-01), Kakimi
patent: 5673233 (1997-09-01), Wright et al.
patent: 5923829 (1999-07-01), Ishii et al.

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